公开(公告)号：US20160314823A1

公开(公告)日：2016-10-27

申请号：US14693769

申请日：2015-04-22

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Kallol Mazumder

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G06F9/30156 ,  G11C7/109 ,  G11C2207/2272

Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

Abstract translation: 公开了用于减少多个命令移位器的装置和方法。 示例性设备包括编码器电路，等待时间移位器电路和解码器电路。 编码器电路可以被配置为对命令进行编码，其中根据命令类型对命令进行编码，并且耦合到编码器电路的等待时间移位器电路可被配置为为已编码的命令提供等待时间。 耦合到等待时间移位器电路的解码器电路可以被配置为对编码的命令进行解码，并提供解码的命令以执行与解码的命令的命令类型相关联的存储器操作。

公开(公告)号：US09294105B2

公开(公告)日：2016-03-22

申请号：US14083875

申请日：2013-11-19

Applicant: Micron Technology, Inc.

Inventor： Tyler J. Gomm ,  Debra Bell

IPC: H03L7/08 ,  G11C7/22 ,  H03L7/081

CPC classification number: H03L7/0802 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814

Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

公开(公告)号：US10789182B2

公开(公告)日：2020-09-29

申请号：US16726523

申请日：2019-12-24

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F15/00 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US10268602B2

公开(公告)日：2019-04-23

申请号：US15280611

申请日：2016-09-29

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F12/02 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US20180122439A1

公开(公告)日：2018-05-03

申请号：US15857597

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Kallol Mazumder

IPC: G11C7/22 ,  G06F9/30 ,  G11C7/10

CPC classification number: G11C7/22 ,  G06F9/30156 ,  G11C7/109 ,  G11C2207/2272

Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

公开(公告)号：US10825492B2

公开(公告)日：2020-11-03

申请号：US16416425

申请日：2019-05-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra Bell ,  Kallol Mazumder

IPC: G11C7/10 ,  G11C7/22 ,  G06F9/30

Abstract: Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.

公开(公告)号：US10521366B2

公开(公告)日：2019-12-31

申请号：US16400739

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F12/10 ,  G06F13/12 ,  G06F13/40 ,  G06F13/28

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US20190258592A1

公开(公告)日：2019-08-22

申请号：US16400739

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F13/12 ,  G06F13/40 ,  G06F13/28

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US10339071B2

公开(公告)日：2019-07-02

申请号：US16192509

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F12/00 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US20200133893A1

公开(公告)日：2020-04-30

申请号：US16726523

申请日：2019-12-24

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F13/12 ,  G06F13/40 ,  G06F13/28

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.