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公开(公告)号:US10482979B1
公开(公告)日:2019-11-19
申请号:US16119715
申请日:2018-08-31
Applicant: Micron Technology, Inc.
Inventor: Matthew D. Rowley , Dustin J. Carter
Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.
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公开(公告)号:US10419574B2
公开(公告)日:2019-09-17
申请号:US15684831
申请日:2017-08-23
Applicant: Micron Technology, Inc.
Inventor: Matthew D. Rowley , Mark Bauer
Abstract: A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.
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公开(公告)号:US20190068743A1
公开(公告)日:2019-02-28
申请号:US15684831
申请日:2017-08-23
Applicant: Micron Technology, Inc.
Inventor: Matthew D. Rowley , Mark Bauer
CPC classification number: H04L67/2885 , G06F13/1668 , H04L67/2838 , H04L69/18 , H04W88/06 , H04W88/16
Abstract: A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.
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