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公开(公告)号：US20230075279A1
公开(公告)日：2023-03-09
申请号：US17468264
申请日：2021-09-07
Applicant: Micron Technology, Inc.
Inventor： Suresh Rajgopal , Chulbum Kim , Dustin J. Carter
Abstract: An input/output (I/O) command referencing a logical address of a memory sub-system is received by an active input/output expander (AIOE). The I/O command is received from a memory sub-system controller via the AIOE. The AIOE identifies a physical block address corresponding to the logical block address. The AIOE identifies, among a plurality of memory devices, a memory device associated with the physical block address. The AIOE converts the I/O command received via the serial interface to a parallel interface compliant I/O command. The AIOE sends the parallel interface compliant I/O command to the memory device.
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公开(公告)号：US20210065822A1
公开(公告)日：2021-03-04
申请号：US17097447
申请日：2020-11-13
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley , Dustin J. Carter
Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.
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公开(公告)号：US12189958B2
公开(公告)日：2025-01-07
申请号：US17898160
申请日：2022-08-29
Applicant: Micron Technology, Inc.
Inventor： Chulbum Kim , Sundararajan Sankaranarayanan , Xiangyu Tang , Dustin J. Carter
IPC: G06F3/06
Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.
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4.发明授权公开(公告)号：US11347415B2
公开(公告)日：2022-05-31
申请号：US17135476
申请日：2020-12-28
Applicant: Micron Technology, Inc.
Inventor： Suresh Rajgopal , Henrico L. Yahja , Steven Eskildsen , Dustin J. Carter
IPC: G06F3/06
Abstract: A selection device includes a multiplexer component, an input channel configured to couple at least the multiplexer to the memory sub-system controller, and a set of output channels coupled to the multiplexer component. Each of the set of output channels is further coupled to a respective memory device of a set of memory devices. Each of the set of output channels is configured to transmit data between the multiplexer component and the respective memory device. The selection device further includes a decoder component that is coupled to the input channel and each of the set of memory devices. The decoder component is configured to receive, from the memory sub-system controller via the input channel, a signal including a first signal portion configured to enable the decoder component and a second signal portion configured to identify a particular output channel of the set of output channels that is to transmit the data between the multiplexer component and the corresponding memory device. The decoder component is to decode the received signal and transmit the decoded signal to each of the set of memory devices. The decoded signal is to enable the transmission of the data between the multiplexer and the corresponding memory device via the particular output channel.
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公开(公告)号：US20230359390A1
公开(公告)日：2023-11-09
申请号：US17735583
申请日：2022-05-03
Applicant: Micron Technology, Inc.
Inventor： Jose Rey C. De Luna , Suresh Rajgopal , Jeremy Wayne Butterfield , Dustin J. Carter
IPC: G06F3/06
CPC classification number: G06F3/0656 , G06F3/0659 , G06F3/0629 , G06F3/0604 , G06F3/0679
Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide a configurable buffer device. The configuration buffer device is coupled between a processing device and a set of memory components. The configurable buffer device can be configured based on configuration data to couple a first quantity of front-side channels to a second quantity of back-side channels. The configuration data can be received from an external source, such as the processing device, or can be stored in a configuration register at manufacture. The configuration data can also be generated or determined based on one or more pins of the buffer device that control how many font-side channels and how many back-side channels to enable/disable.
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Patent Agency Ranking
公开(公告)号：US11468171B2
公开(公告)日：2022-10-11
申请号：US17104876
申请日：2020-11-25
Applicant: Micron Technology, Inc.
Inventor： Robert W. Strong , Dustin J. Carter , Neil Levine
Abstract: A variety of applications can include apparatus and/or methods of controlling a secure boot mode for a memory system. In an embodiment, a system includes a memory component and a processing device, where the processing device is configured to control a boot process for the system to operate the memory component and perform a cryptographic verification with a host to conduct an authentication of the host. The processing device can interact with the host, in response to the authentication, to receive a setting to control the boot process in a secure boot mode. The processing can interact with another processing device of the system to store the setting and to receive a secure boot signal from the other processing device, where the secure boot signal is a signal to assert or de-assert the secure boot mode depending on a value of the setting. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US10861567B2
公开(公告)日：2020-12-08
申请号：US16684924
申请日：2019-11-15
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley , Dustin J. Carter
Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.
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公开(公告)号：US20200090765A1
公开(公告)日：2020-03-19
申请号：US16684924
申请日：2019-11-15
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Rowley , Dustin J. Carter
Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.
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9.发明申请公开(公告)号：US20190354301A1
公开(公告)日：2019-11-21
申请号：US15982978
申请日：2018-05-17
Applicant: Micron Technology, Inc.
Inventor： Suresh Rajgopal , Henrico L. Yahja , Steven Eskildsen , Dustin J. Carter
IPC: G06F3/06
Abstract: A selection device can be operatively coupled with non-volatile memory devices. Enable signals that are based on an architecture of non-volatile memory devices can be received. Data can be transmitted to the non-volatile memory devices based on the enable signals that are based on the architecture of the non-volatile memory devices.
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公开(公告)号：US20250077086A1
公开(公告)日：2025-03-06
申请号：US18950798
申请日：2024-11-18
Applicant: Micron Technology, Inc.
Inventor： Chulbum Kim , Sundararajan Sankaranarayanan , Xiangyu Tang , Dustin J. Carter
IPC: G06F3/06
Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, wherein the memory sub-system controller provides a plurality of channel mappings, wherein a first channel mapping of the plurality of channel mappings identifies a first controller channel of the plurality of controller channels and one or more first memory channels of a plurality of memory channels, and wherein a second channel mapping of the plurality of channel mappings identifies a second controller channel of the plurality of controller channels and one or more second memory channels of the plurality of memory channels; one or more memory devices comprising the plurality of memory channels, wherein the one or more memory devices comprise a plurality of memory dies, wherein each memory channel of the plurality of memory channels corresponds to a respective one of the plurality of memory dies; and a channel switch circuit coupled between the plurality of the controller channels and the plurality of memory channels, wherein each controller channel of the plurality of the controller channels is capable to be mapped to the plurality of memory channels for data routing.
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