公开(公告)号：US07856607B2

公开(公告)日：2010-12-21

申请号：US11934146

申请日：2007-11-02

申请人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

发明人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F11/24 ,  G01R31/31835

摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.

摘要翻译： 一种提高高速结构测试（ASST）实用性的系统。 在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。 第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。 第三种方法是选择逻辑电路的节点作为关键性分析的函数。 第四种装置根据所选节点的临界概率来选择定时路径。 第五装置为每个所选定时路径生成ASST模式。 提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

公开(公告)号：US20090119629A1

公开(公告)日：2009-05-07

申请号：US11934146

申请日：2007-11-02

申请人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

发明人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F11/24 ,  G01R31/31835

摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.

摘要翻译： 一种提高高速结构测试（ASST）实用性的系统。 在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。 第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。 第三种方法是选择逻辑电路的节点作为关键性分析的函数。 第四种装置根据所选节点的临界概率来选择定时路径。 第五装置为每个所选定时路径生成ASST模式。 提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

公开(公告)号：US09157956B2

公开(公告)日：2015-10-13

申请号：US13614564

申请日：2012-09-13

申请人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

发明人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

IPC分类号： G06F17/50 ,  G01R31/317 ,  G01R31/30

CPC分类号： G01R31/31718 ,  G01R31/3008

摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非瞬时存储介质存储电压仓的边界作为速度分组测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

公开(公告)号：US08448110B2

公开(公告)日：2013-05-21

申请号：US12625139

申请日：2009-11-24

申请人： Peter A. Habitz ,  Eric A. Foreman ,  Gustavo E. Tellez

发明人： Peter A. Habitz ,  Eric A. Foreman ,  Gustavo E. Tellez

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5031 ,  G06F2217/12 ,  G06F2217/84 ,  Y02P90/265

摘要： A method receives an initial circuit design. The circuit design includes at least one path having at least one beginning point comprising a source, at least one ending point comprising a sink, and one or more circuit elements between the source and the sink. The method evaluates timing performance parameter sensitivities to manufacturing variations of each of the elements to identify how much each element will increase or decrease the timing performance parameter of the path for each change in each manufacturing variable associated with manufacturing the elements. Further, the method alters the elements within the path until elements that produce positive changes to the timing performance parameter for a given manufacturing variable change approximately equals (in magnitude) elements that produce negative changes to the timing performance parameter for the given manufacturing variable change, to produce an altered circuit design.

摘要翻译： 一种方法接收初始电路设计。 该电路设计包括至少一个路径，该至少一个路径具有包括源的至少一个起始点，包括宿的至少一个终点以及源和宿之间的一个或多个电路元件。 该方法评估每个元件的制造变化的时序性能参数灵敏度，以识别每个元件将增加或减少与制造元件相关联的每个制造变量中的每个变化的路径的时序性能参数。 此外，该方法改变路径内的元素，直到产生对于给定制造变量的定时性能参数的正变化的元素大致等于（在大小上）元素，该元素对于给定的制造变量变化而对定时性能参数产生负变化， 以产生改变的电路设计。

公开(公告)号：US20140074422A1

公开(公告)日：2014-03-13

申请号：US13614564

申请日：2012-09-13

申请人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

发明人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

IPC分类号： G06F17/50 ,  G06F19/00 ,  G01R31/317

CPC分类号： G01R31/31718 ,  G01R31/3008

摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非瞬时存储介质存储电压仓的边界作为速度分组测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

公开(公告)号：US20110126163A1

公开(公告)日：2011-05-26

申请号：US12625139

申请日：2009-11-24

申请人： Peter A. Habitz ,  Eric A. Foreman ,  Gustavo E. Tellez

发明人： Peter A. Habitz ,  Eric A. Foreman ,  Gustavo E. Tellez

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/12 ,  G06F2217/84 ,  Y02P90/265

摘要： A method receives an initial circuit design. The circuit design includes at least one path having at least one beginning point comprising a source, at least one ending point comprising a sink, and one or more circuit elements between the source and the sink. The method evaluates timing performance parameter sensitivities to manufacturing variations of each of the elements to identify how much each element will increase or decrease the timing performance parameter of the path for each change in each manufacturing variable associated with manufacturing the elements. Further, the method alters the elements within the path until elements that produce positive changes to the timing performance parameter for a given manufacturing variable change approximately equals (in magnitude) elements that produce negative changes to the timing performance parameter for the given manufacturing variable change, to produce an altered circuit design.

摘要翻译： 一种方法接收初始电路设计。 该电路设计包括至少一个路径，该至少一个路径具有包括源的至少一个起始点，包括宿的至少一个终点以及源和宿之间的一个或多个电路元件。 该方法评估每个元件的制造变化的时序性能参数灵敏度，以识别每个元件将增加或减少与制造元件相关联的每个制造变量中的每个变化的路径的时序性能参数。 此外，该方法改变路径内的元素，直到产生对于给定制造变量的定时性能参数的正变化的元素大致等于（在大小上）元素，该元素对于给定的制造变量变化而对定时性能参数产生负变化， 以产生改变的电路设计。

公开(公告)号：US07418689B2

公开(公告)日：2008-08-26

申请号：US10908102

申请日：2005-04-27

申请人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

发明人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

公开(公告)号：US20080195993A1

公开(公告)日：2008-08-14

申请号：US12107158

申请日：2008-04-22

申请人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

发明人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

公开(公告)号：US07865861B2

公开(公告)日：2011-01-04

申请号：US12107158

申请日：2008-04-22

申请人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

发明人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

公开(公告)号：US07823115B2

公开(公告)日：2010-10-26

申请号：US12108629

申请日：2008-04-24

申请人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

发明人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。