SELECTIVE OVERRIDE OF CACHE COHERENCE IN MULTI-PROCESSOR COMPUTER SYSTEMS

    公开(公告)号:US20210097000A1

    公开(公告)日:2021-04-01

    申请号:US16589698

    申请日:2019-10-01

    Abstract: Various example embodiments are related to cache coherence in multiprocessor computer systems. Various example embodiments are configured to support efficient cache coherence in multiprocessor computer systems. Various example embodiments are configured to support efficient cache coherence in multiprocessor computer systems based on support for selective override of cache coherence by processors in multiprocessor computer systems. Various example embodiments for supporting selective override of cache coherence in multiprocessor computer systems are configured to support selective override of cache coherence in processors of a multiprocessor computer system based on programmable approaches in the processors for selective overriding of cache coherence and based on use by the processors of snooping-based cache coherence protocols with capabilities for supporting selective overriding of cache coherence.

    DYNAMIC CONTROL OF PROCESSOR INSTRUCTION SETS

    公开(公告)号:US20210049017A1

    公开(公告)日:2021-02-18

    申请号:US17089085

    申请日:2020-11-04

    Abstract: Various example embodiments for supporting message processing are presented. Various example embodiments for supporting message processing are configured to support message processing by a processor. Various example embodiments for supporting message processing by a processor are configured to support message processing by the processor based on dynamic control over processor instruction sets of the processor.

    MULTICAST RENDEZVOUS POINT DISCOVERY

    公开(公告)号:US20250047587A1

    公开(公告)日:2025-02-06

    申请号:US18362621

    申请日:2023-07-31

    Abstract: Various example embodiments for supporting discovery of multicast rendezvous points for multicast trees are presented herein. Various example embodiments for supporting discovery of multicast rendezvous points for multicast trees may be configured to provide a generic capability for discovery of multicast rendezvous points in various types of communication networks which may utilize various communication protocols. Various example embodiments for supporting discovery of multicast rendezvous points for multicast trees may be configured to support discovery of multicast rendezvous points for multicast trees based on advertising of rendezvous point to multicast group mappings for multicast trees. Various example embodiments for supporting discovery of multicast rendezvous points for multicast trees may be configured to support discovery of multicast rendezvous points for multicast trees based on advertising of rendezvous point to multicast group mappings for multicast trees by flooding/broadcasting the rendezvous point to multicast group mappings through a routing protocol.

    Egress rerouting of packets at a communication device

    公开(公告)号:US12126528B2

    公开(公告)日:2024-10-22

    申请号:US18189295

    申请日:2023-03-24

    CPC classification number: H04L45/566 H04L45/22

    Abstract: Various example embodiments for supporting egress rerouting of data packets in communication devices are presented herein. The egress rerouting of a data packet in a communication device may be performed by rerouting a data packet received via an ingress forwarding element of the communication device from a first egress forwarding element of the communication device associated with a primary next-hop for the data packet to a second egress forwarding element of the communication device associated with a secondary next-hop for the data packet.

    Processor micro-operations cache architecture for intermediate instructions

    公开(公告)号:US12061907B2

    公开(公告)日:2024-08-13

    申请号:US17704127

    申请日:2022-03-25

    CPC classification number: G06F9/30047 G06F9/30145 G06F12/0862 G06F12/0895

    Abstract: Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments may be configured to support a micro-architecture for a micro-operations cache (UC) of a processor. Various example embodiments for supporting a micro-architecture for a UC of a processor may be configured to implement the UC of a processor using an intermediate vector UC (IV-UC). Various example embodiments for supporting an IV-UC for a processor may be configured to support a processor including an IV-UC where the IV-UC includes a micro-operations cache (UC) configured to store a cache line including sets of micro-operations (UOPs) from instructions decoded by the processor and an intermediate vector cache (IVC) configured to store indications of locations of the sets of UOPs in the cache line of the UC for intermediate instructions of the cache line of the UC.

    MULTI-MODE INDEXED CACHE IN A PROCESSOR
    56.
    发明公开

    公开(公告)号:US20240241832A1

    公开(公告)日:2024-07-18

    申请号:US18097421

    申请日:2023-01-16

    CPC classification number: G06F12/0864 G06F12/0895

    Abstract: Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments for supporting processor capabilities may be configured to support a multi-mode indexed cache for a processor. Various example embodiments for supporting a multi-mode indexed cache for a processor may be configured to support a multi-mode indexed cache configured as a set associative cache having a plurality of sets, where the cache is configured to support multiple indexing modes for indexing memory blocks such that, for a memory operation for a memory block, the multiple indexing modes are configured to cause selection of different ones of the plurality of sets of the cache for the memory operation for the given memory block.

    DYNAMIC BRANCH CAPABLE MICRO-OPERATIONS CACHE

    公开(公告)号:US20240118896A1

    公开(公告)日:2024-04-11

    申请号:US17960583

    申请日:2022-10-05

    CPC classification number: G06F9/3844 G06F9/30047 G06F9/30058

    Abstract: Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments for supporting processor capabilities may be configured to support increased efficiency in utilization of a micro-operations cache (UC) of a processor. Various example embodiments for supporting increased efficiency in utilization of a UC of a processor may be configured to support increased efficiency in utilization of the UC of the processor based on configuration of the processor such that UC lines created by a prediction window (PW) during execution of a set of instructions by the processor are not invalidated on misprediction of a branch instruction in the set of instructions.

    SEQUENCING OF LABELED PACKETS
    58.
    发明公开

    公开(公告)号:US20230308387A1

    公开(公告)日:2023-09-28

    申请号:US17701982

    申请日:2022-03-23

    CPC classification number: H04L45/50 H04L47/34

    Abstract: Various example embodiments for supporting sequencing of labeled packets are presented herein. Various example embodiments for supporting sequencing of labeled packets may be configured to support sequencing of labeled packet based on use of a multiprotocol label switching sequence header. Various example embodiments for supporting sequencing of labeled packets may be configured to support sequencing of labeled packet based on use of a multiprotocol label switching sequence header that includes a source identifier of a source of a multiprotocol label switching packet sequence including the multiprotocol label switching packet, a sequence identifier of the multiprotocol label switching packet sequence, and a sequence number of the multiprotocol label switching packet. Various example embodiments for supporting sequencing of labeled packets may be configured to support sequencing of Multiprotocol Label Switching (MPLS) packets.

    Packet routing based on common node protection

    公开(公告)号:US11677658B2

    公开(公告)日:2023-06-13

    申请号:US16575945

    申请日:2019-09-19

    Abstract: Various example embodiments for supporting rerouting of packets in communication networks are presented. Various example embodiments for supporting rerouting of packets in communication networks may be configured to support rerouting of packets based on common node protection. Various example embodiments for supporting rerouting of packets based on common node protection may be configured to support rerouting of source routed packets in packet switched networks. Various example embodiments for supporting rerouting of packets based on common node protection may be configured to support rerouting of source routed packets based on segment routing (SR). Various example embodiments for supporting rerouting of packets based on common node protection may be configured to support rerouting of source routed packets based on SR-Traffic Engineering (SR-TE). Various example embodiments for supporting rerouting of packets based on common node protection may be configured to support fast rerouting (FRR) of source routed packets based on SR-TE.

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