公开(公告)号：US11094103B2

公开(公告)日：2021-08-17

申请号：US16364829

申请日：2019-03-26

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Chun Yu ,  Chihong Zhang ,  Hongjiang Shang ,  Zilin Ying ,  Fei Wei

IPC: G06T15/04 ,  G06F9/54 ,  G06F9/38

Abstract: Example techniques are described for generating graphics content by obtaining texture operation instructions corresponding to a texture operation, in response to determining at least one of insufficient general purpose register space is available for the texture operation or insufficient wave slots are available for the texture operation, generating an indication that the texture operation corresponds to a deferred wave, executing the texture operation, sending, to a texture processor, initial texture sample instructions corresponding to the texture operation that was executed, and receiving texture mapped data corresponding to the initial texture sample instructions.

公开(公告)号：US10796478B2

公开(公告)日：2020-10-06

申请号：US16143260

申请日：2018-09-26

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber

IPC: G06T17/00 ,  G06T15/40 ,  G06T15/04 ,  G06T1/20

Abstract: A method, a computer-readable medium, and an apparatus are provided. The apparatus may be a GPU. The GPU generates first visibility information during a visibility pass associated with an application requested depth pre-pass. In addition, the GPU renders an application requested color pass based on the first visibility information generated during the visibility pass associated with the application requested depth pre-pass.

公开(公告)号：US20190197651A1

公开(公告)日：2019-06-27

申请号：US15850907

申请日：2017-12-21

Applicant: QUALCOMM Incorporated

Inventor： Brendon Lewis Johnson ,  Andrew Evan Gruber ,  Jay Chunsup Yun ,  Rahul Gulati ,  Donghyun Kim ,  Alex Kwang Ho Jong

IPC: G06T1/20 ,  G06T1/60 ,  G06F11/10

CPC classification number: G06T1/20 ,  B60K35/00 ,  B60K2370/21 ,  B60R1/00 ,  B60R2300/30 ,  G06F11/1004 ,  G06T1/60 ,  G06T7/001 ,  G06T2207/30108 ,  G09G5/363 ,  G09G2330/08 ,  G09G2330/10 ,  G09G2330/12 ,  G09G2380/10 ,  G09G2380/12

Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.

公开(公告)号：US20190171538A1

公开(公告)日：2019-06-06

申请号：US15832042

申请日：2017-12-05

Applicant: QUALCOMM Incorporated

Inventor： Rahul Gulati ,  Andrew Evan Gruber ,  Brendon Lewis Johnson ,  Jay Chunsup Yun ,  Donghyun Kim ,  Alex Kwang Ho Jong ,  Anshuman Saxena

IPC: G06F11/22 ,  G06T1/20 ,  G06T15/00 ,  G06F11/07

Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.

公开(公告)号：US20190050958A1

公开(公告)日：2019-02-14

申请号：US16103336

申请日：2018-08-14

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Pramod Vasant Argade ,  Jing Wu

IPC: G06T1/20 ,  G06F9/38 ,  G06T5/00 ,  G06F9/30

Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.

公开(公告)号：US10133572B2

公开(公告)日：2018-11-20

申请号：US14268215

申请日：2014-05-02

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Lin Chen ,  Yun Du ,  Alexei Vladimirovich Bourd

IPC: G06F9/30 ,  G06F9/38

Abstract: A SIMD processor may be configured to determine one or more active threads from a plurality of threads, select one active thread from the one or more active threads, and perform a divergent operation on the selected active thread. The divergent operation may be a serial operation.

公开(公告)号：US10089708B2

公开(公告)日：2018-10-02

申请号：US15141519

申请日：2016-04-28

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Lin Chen ,  Liang Li ,  Chunhui Mei

IPC: G06T15/80 ,  G06T15/04 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: A texture unit of a graphics processing unit (GPU) may receive a texture data. The texture unit may receive the texture data from the memory. The texture unit may also multiply, by a multiplier circuit of the texture unit, the texture data by at least one constant, where the constant is not associated with a filtering operation, and where the texture data comprises at least one texel. The texture unit may also output, by the texture unit, a result of multiplying the texture data by the at least one constant.

公开(公告)号：US20180232846A1

公开(公告)日：2018-08-16

申请号：US15432170

申请日：2017-02-14

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Lin Chen

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005

Abstract: A GPU may be configured to detect and nullify unnecessary instructions. Nullifying unnecessary instructions include overwriting a detected unnecessary instruction with a no operation (NOP) instruction. In another example, nullifying unnecessary instructions may include writing a value to a 1-bit instruction memory. Each bit of the 1-bit instruction memory may be associated with a particular instruction of the draw call. If the 1-bit instruction memory has a true value (e.g., 1), the GPU is configured to not execute the particular instruction.

公开(公告)号：US09818170B2

公开(公告)日：2017-11-14

申请号：US14566423

申请日：2014-12-10

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber

IPC: G06T1/60 ,  G06F13/28 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F13/28 ,  G06T1/20 ,  G06T2200/28 ,  Y02D10/14

Abstract: This disclosure describes techniques for processing unaligned block transfer (BLT) commands. The techniques of this disclosure may involve converting an unaligned BLT command into multiple aligned BLT commands, where the multiple aligned BLT commands may collectively produce the same resulting memory state as that which would have been produced by the unaligned BLT command. The techniques of this disclosure may allow the benefits of relatively low-power GPU-accelerated BLT processing may be achieved for unaligned BLT commands without requiring a CPU to pre-process and/or post-process the underlying unaligned surfaces. In this way, the performance and/or power consumption associated with processing unaligned BLT commands in an alignment-constrained GPU-based system may be improved.

公开(公告)号：US09665370B2

公开(公告)日：2017-05-30

申请号：US14462932

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Lin Chen ,  Andrew Evan Gruber ,  Chihong Zhang ,  Chun Yu

IPC: G06T15/00 ,  G06F9/30 ,  G06T1/20 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F9/30098 ,  G06F8/441 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3828 ,  G06F9/3859 ,  G06T1/20 ,  G06T2200/28

Abstract: Techniques are described in which an indication is included to indicate a last use of an intermediate value generated as part of determining a final value is not be stored in a general purpose register (GPR). A processing unit avoids storing the intermediate value in the GPR based on the indication because the intermediate value is no longer needed for determining the final value.