公开(公告)号：US20060095613A1

公开(公告)日：2006-05-04

申请号：US10977952

申请日：2004-10-29

申请人： Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

发明人： Ramanand Venkata ,  Rakesh Patel ,  Chong Lee

IPC分类号： G06F13/38

CPC分类号： G06F13/385

摘要： Eight-bit ten-bit (8B10B) coding is provided in a hard intellectual property (IP) block with the capability of supporting a greater range of data rates (e.g., data rates less than, equal to, and greater than 3.125 Gbps). Each channel of high speed serial interface circuitry includes receiver circuitry having two 8B10B decoders and transmitter circuitry having two 8B10B encoders. The receiver and transmitter circuitry can be configured to operate in one of three modes of operation: cascade mode, dual channel mode, and single channel mode.

摘要翻译： 在具有支持更大范围的数据速率（例如，数据速率小于等于并且大于3.125Gbps）的能力的硬知识产权（IP）块中提供八位十位（8B10B）编码。 高速串行接口电路的每个通道包括具有两个8B10B解码器和具有两个8B10B编码器的发射机电路的接收机电路。 接收器和发射器电路可以配置为在三种工作模式之一下工作：级联模式，双通道模式和单通道模式。

公开(公告)号：US20050007996A1

公开(公告)日：2005-01-13

申请号：US10835081

申请日：2004-04-28

申请人： Ramanand Venkata ,  Chong Lee ,  Rakesh Patel

发明人： Ramanand Venkata ,  Chong Lee ,  Rakesh Patel

IPC分类号： H03K19/177 ,  H04Q11/04 ,  H04J3/06

CPC分类号： H03K19/17744 ,  H03K19/17732 ,  H04J3/1617 ,  H04J2203/0082 ,  H04J2203/0094

摘要： A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

摘要翻译： 可编程逻辑器件（“PLD”）包括通信接口电路，其可以支持任何广泛的通信协议，包括分组超声波（“POS-5”）和8位/ 10比特（“8B10B”）协议 。 接口电路包括至少部分硬连线以执行特定类型的功能的各种功能块，但是在至少许多情况下也可部分地可编程以允许基本功能适应各种协议。 对各种功能块之间，之间和/或周围的信号的路由也优选地至少可部分地可编程以便于以各种方式组合功能块来支持各种协议。

公开(公告)号：US06842034B1

公开(公告)日：2005-01-11

申请号：US10612253

申请日：2003-07-01

申请人： Vinson Chan ,  Chong Lee ,  Rakesh Patel ,  Ramanand Venkata ,  Binh Ton

发明人： Vinson Chan ,  Chong Lee ,  Rakesh Patel ,  Ramanand Venkata ,  Binh Ton

IPC分类号： H03K19/177 ,  H03K19/00

CPC分类号： H03K19/17752 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17744

摘要： Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.

摘要翻译： 提供了PLD的核心PLD结构与驻留在其中的嵌入式IP构建块之间的改进的通信和改进的通信接口。 根据本发明的电路可以包括PLD核心结构和嵌入式IP构建块之间的至少两个不同的信号路径。 这两个路径中的一个或两者可以用于嵌入式IP构建块的配置和/或实现。