公开(公告)号：US07960992B2

公开(公告)日：2011-06-14

申请号：US12392387

申请日：2009-02-25

申请人： Ramon S. Co ,  Kevin J. Sun

发明人： Ramon S. Co ,  Kevin J. Sun

IPC分类号： G01R31/20

CPC分类号： G11C29/56 ,  B65G47/71 ,  G11C5/04 ,  G11C29/56016

摘要： A conveyor-stack test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. A loader-unloader removes tested memory modules from test sockets on the motherboards and inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader-unloader to an elevator. The elevator raises or lowers the motherboards to different levels in a conveyor stack with multiple levels of conveyors each with many test stations. The motherboards move along conveyors in the conveyor stack until reaching test stations. A retractable connector from the test station extends to make contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns.

摘要翻译： 输送机堆叠测试系统具有测试内存模块的主板。 主板不是静止的，而是位于沿传送带移动的活动托盘内。 装载机卸载程序从主板上的测试插槽中删除测试的内存模块，并使用机械臂将未测试的内存模块插入主板。 输送机将主板从装载机卸载机运送到电梯。 电梯将主板升高或降低到输送机堆叠中的不同水平，多层输送机各有许多测试站。 主板沿着输送机堆栈中的输送机移动，直至到达测试站。 来自测试台的可伸缩连接器延伸以与母板连接器接触，以对主板供电，然后测试存储器模块。 测试结果从测试台传送到主机控制器，主机控制器指示装载机卸载机在主板返回后对测试的内存模块进行排序。

公开(公告)号：US07917327B2

公开(公告)日：2011-03-29

申请号：US12831777

申请日：2010-07-07

申请人： Ramon S. Co ,  Tat Leung Lai ,  Calvin G. Leong

发明人： Ramon S. Co ,  Tat Leung Lai ,  Calvin G. Leong

IPC分类号： G06F19/00 ,  G06F17/40

CPC分类号： B25J9/1666 ,  B25J9/16 ,  G05B19/4182 ,  Y02P90/083

摘要： Two robotic arms roam in separate, non-overlapping areas of a test station, avoiding collisions. A traveling buffer moves along x-tracks between a front position and a back position. In the front position, a first robotic arm loads IC chips from an input tray or stacker into buffer cavities in the traveling buffer. The traveling buffer then moves along the x-tracks to the back position, where a second robotic arm moves chips from the traveling buffer to test boards for testing. After testing, the second robotic arm moves chips to a second traveling buffer, which then moves along tracks to a front position for unloading by the first robotic arm. Two traveling buffers may move on the same tracks in a loop. The buffer cavities in the traveling buffer move on internal tracks to expand and contract spacing and pitch between the front and back positions to match test-board pitch.

摘要翻译： 两个机器人臂在测试台的分开的，不重叠的区域漫游，避免碰撞。 移动缓冲器沿着前方位置和后方位置之间的x轨道移动。 在前置位置，第一机器臂将IC芯片从输入托盘或堆叠器装载到行进缓冲器中的缓冲腔中。 移动缓冲器然后沿x轨道移动到后部位置，其中第二机器人臂将芯片从行进缓冲器移动到测试板进行测试。 在测试之后，第二机器人臂将芯片移动到第二行进缓冲器，然后第二移动缓冲器沿着轨道移动到前部位置，以由第一机器人臂卸载。 两个移动缓冲器可以在循环中的相同轨道上移动。 移动缓冲器中的缓冲腔在内部轨道上移动以在前后位置之间扩展和收缩间距和间距，以匹配测试板间距。

公开(公告)号：US07884631B2

公开(公告)日：2011-02-08

申请号：US12392401

申请日：2009-02-25

申请人： Ramon S. Co ,  Kevin J. Sun

发明人： Ramon S. Co ,  Kevin J. Sun

IPC分类号： G01R31/02

CPC分类号： G11C29/56 ,  G11C29/56016

摘要： A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors.

摘要翻译： 停车结构测试系统具有测试内存模块的主板。 主板不是静止的，而是位于沿传送带移动的活动托盘内。 卸载器从主板上的测试插槽中删除测试的内存模块，并且加载器使用机械​​臂将未测试的内存模块插入主板。 输送机将主板从装载机运送到停车和测试结构。 电梯将主板升高或降低到停车和测试结构中的不同停车位。 主板从电梯移动到停车位的测试站。 来自测试台的可伸缩连接器与母板连接器接触，为主板供电，然后测试内存模块。 测试结果从测试台传送到主机控制器，主机控制器指示装载机卸载机在主板通过电梯和输送机返回后对被测试的存储器模块进行排序。

公开(公告)号：US20100274517A1

公开(公告)日：2010-10-28

申请号：US12831777

申请日：2010-07-07

申请人： Ramon S. Co ,  Tat Leung Lai ,  Calvin G. Leong

发明人： Ramon S. Co ,  Tat Leung Lai ,  Calvin G. Leong

IPC分类号： G06F19/00 ,  G05B19/418

CPC分类号： B25J9/1666 ,  B25J9/16 ,  G05B19/4182 ,  Y02P90/083

摘要： Two robotic arms roam in separate, non-overlapping areas of a test station, avoiding collisions. A traveling buffer moves along x-tracks between a front position and a back position. In the front position, a first robotic arm loads IC chips from an input tray or stacker into buffer cavities in the traveling buffer. The traveling buffer then moves along the x-tracks to the back position, where a second robotic arm moves chips from the traveling buffer to test boards for testing. After testing, the second robotic arm moves chips to a second traveling buffer, which then moves along tracks to a front position for unloading by the first robotic arm. Two traveling buffers may move on the same tracks in a loop. The buffer cavities in the traveling buffer move on internal tracks to expand and contract spacing and pitch between the front and back positions to match test-board pitch.

摘要翻译： 两个机器人臂在测试台的分开的，不重叠的区域漫游，避免碰撞。 移动缓冲器沿着前方位置和后方位置之间的x轨道移动。 在前置位置，第一机器臂将IC芯片从输入托盘或堆叠器装载到行进缓冲器中的缓冲腔中。 移动缓冲器然后沿x轨道移动到后部位置，其中第二机器人臂将芯片从行进缓冲器移动到测试板进行测试。 在测试之后，第二机器人臂将芯片移动到第二行进缓冲器，然后第二移动缓冲器沿着轨道移动到前部位置，以由第一机器人臂卸载。 两个移动缓冲器可以在循环中的相同轨道上移动。 移动缓冲器中的缓冲腔在内部轨道上移动以在前后位置之间扩展和收缩间距和间距，以匹配测试板间距。

公开(公告)号：US20100218050A1

公开(公告)日：2010-08-26

申请号：US12392401

申请日：2009-02-25

申请人： Ramon S. Co ,  Kevin J. Sun

发明人： Ramon S. Co ,  Kevin J. Sun

IPC分类号： G06F11/273

CPC分类号： G11C29/56 ,  G11C29/56016

摘要： A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors.

摘要翻译： 停车结构测试系统具有测试内存模块的主板。 主板不是静止的，而是位于沿传送带移动的活动托盘内。 卸载器从主板上的测试插槽中删除测试的内存模块，并且加载器使用机械​​臂将未测试的内存模块插入主板。 输送机将主板从装载机运送到停车和测试结构。 电梯将主板升高或降低到停车和测试结构中的不同停车位。 主板从电梯移动到停车位的测试站。 来自测试台的可伸缩连接器与母板连接器接触，为主板供电，然后测试内存模块。 测试结果从测试台传送到主机控制器，主机控制器指示装载机卸载机在主板通过电梯和输送机返回后对被测试的存储器模块进行排序。

公开(公告)号：US07688929B2

公开(公告)日：2010-03-30

申请号：US11692472

申请日：2007-03-28

申请人： Ramon S. Co

发明人： Ramon S. Co

IPC分类号： H03D3/24

CPC分类号： H03L7/0814 ,  H03C3/0966 ,  H03L2207/50 ,  H04L27/22

摘要： Multi-phase clocks are used to encode and decode signals that are phase-modulated. The input signal is phase-compared with a feedback clock. Phase differences increment or decrement an up/down counter. The count value from the up/down counter is applied to a phase rotator, which selects one clock phase from a bank of multi-phase clocks. The multi-phase clocks have the same frequency, but are offset in phase from each other. An output divider divides the selected multi-phase clock to generate a phase-modulated output. A feedback divider divides a fixed-phase clock from the multi-phase clocks to generate the feedback clock. An analog or a digital front-end may be used to convert analog inputs to digital signals to increment or decrement the counter, or to encode multiple digital bits as phase assignments. For a de-modulator, a digital-to-analog converter (DAC) or a digital decoder produces the final output from the count of the up/down counter.

摘要翻译： 多相时钟用于对相位调制的信号进行编码和解码。 输入信号与反馈时钟进行相位比较。 相位差递增或递减上/下计数器。 来自递增/递减计数器的计数值被应用于从一组多相时钟选择一个时钟相位的相位旋转器。 多相时钟具有相同的频率，但彼此相位偏移。 输出分频器分频所选择的多相时钟以产生相位调制输出。 反馈分频器将固定相位时钟与多相时钟分频，以产生反馈时钟。 模拟或数字前端可以用于将模拟输入转换为数字信号，以递增或递减计数器，或将多个数字位编码为相位分配。 对于解调器，数/模转换器（DAC）或数字解码器从上/下计数器的计数产生最终输出。

公开(公告)号：US07509532B2

公开(公告)日：2009-03-24

申请号：US10249841

申请日：2003-05-12

申请人： Ramon S. Co ,  Tat Leung Lai ,  David Da-Wei Sun

发明人： Ramon S. Co ,  Tat Leung Lai ,  David Da-Wei Sun

IPC分类号： G06F11/00

CPC分类号： G01R31/01 ,  G01R31/31713 ,  G01R31/31905 ,  G11C5/04 ,  G11C29/028 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5004 ,  H05K1/141

摘要： A test system for testing memory modules uses vertically-mounted personal computer (PC) motherboards. Many test adaptor boards that contain test sockets for testing memory modules are mounted horizontally across a test bench. Each test adaptor board connects to a motherboard that tests the memory modules in the test sockets. The motherboard is mounted below and perpendicularly to the test adaptor board. The motherboard is modified to extend the memory bus to edge contact pads along an edge of the motherboard. An edge socket on the test adaptor board mates with the edge contact pads to make electrical connection. A robotic arm inserts a memory module into the test socket, allowing the vertically-mounted motherboard to execute programs to test the memory module.

摘要翻译： 用于测试存储器模块的测试系统使用垂直安装的个人计算机（PC）主板。 包含用于测试内存模块的测试插槽的许多测试适配器板水平安装在测试台上。 每个测试适配器板连接到测试插槽中的内存模块的主板。 主板安装在测试适配器板的下方并垂直。 主板被修改为沿主板边缘将内存总线扩展到边缘接触焊盘。 测试适配器板上的边缘插座与边缘接触垫匹配以进行电气连接。 机器手臂将内存模块插入测试插座，允许垂直安装的主板执行程序来测试内存模块。

公开(公告)号：US07477526B1

公开(公告)日：2009-01-13

申请号：US11306481

申请日：2005-12-29

申请人： Ramon S. Co

发明人： Ramon S. Co

IPC分类号： H05K1/11

CPC分类号： G11C5/04

摘要： A branching fully-buffered memory module has one uplink port and two downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the two downlink ports to two branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory module has re-timing and re-synchronizing buffers that repeat frames to the two downlink ports. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin count. Sync patterns are added to the start of frames to detect any collisions on bidirectional lines. Point-to-point bus segments have only two endpoints despite branching by the branching AMB. Latency from the host processor to the last memory module is reduced by branching compared with a serial daisy-chain of memory modules.

摘要翻译： 分支全缓冲存储器模块具有一个上行链路端口和两个下行链路端口。 在主机处理器发送的下游发送的帧在上行链路端口上被接收并重复到两个下行链路端口到存储器模块的两个分支。 通过下行链路端口上的存储器模块向处理器上行发送的帧被重复到上行链路端口。 分支存储器模块上的分支高级存储器缓冲器（AMB）具有对两个下行链路端口重复帧的重新定时和重新同步缓冲器。 分开的北行和南行车道可能会被双向通道取代，以减少针数。 同步模式被添加到帧的开始，以检测双向线路上的任何冲突。 点对点总线段只有两个端点，尽管分支AMB分支。 与内存模块的串行菊花链相比，从主处理器到最后一个内存模块的延迟减少了。

公开(公告)号：US06351827B1

公开(公告)日：2002-02-26

申请号：US09702018

申请日：2000-10-30

申请人： Ramon S. Co ,  Tat Leung Lai ,  Thang Nguyen

发明人： Ramon S. Co ,  Tat Leung Lai ,  Thang Nguyen

IPC分类号： H02H305

CPC分类号： G01R31/01 ,  G01R31/31713 ,  G01R31/31905 ,  G11C5/04 ,  G11C29/028 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5004 ,  H05K1/141

摘要： Margin testing of memory modules uses a personal computer (PC) motherboard. A test adaptor board has a test socket that receives a memory module under test. Pins from the test adaptor board are plugged into holes of a removed memory-module socket on the motherboard, mounted on the reverse, solder side of the motherboard. The test adapter board has a voltage regulator that controls the power-supply (Vcc) voltage applied to the module under test. A delay circuit on the test adapter board varies the phase delay of a clock to the memory module under test. Margin control signals are generated by a controller card in the PC's expansion slots, to control Vcc and clock delay to the module under test without changing the motherboard's Vcc voltage. The test program executing on the PC motherboard writes to the controller card to adjust voltage and delay, allowing Vcc and setup and hold margins to be tested.

摘要翻译： 内存模块的保证金测试使用个人计算机（PC）主板。 测试适配器板具有接收被测内存模块的测试插座。 来自测试适配器板的引脚插入主板上拆下的内存模块插槽的孔中，安装在主板的反面焊接面上。 测试适配器板具有一个电压调节器，用于控制施加到被测模块的电源（Vcc）电压。 测试适配器板上的延迟电路将时钟的相位延迟改变为被测存储器模块。 边缘控制信号由PC扩展槽中的控制器卡产生，以控制Vcc和测试模块的时钟延迟，而不会改变主板的Vcc电压。 在PC主板上执行的测试程序向控制器卡写入调整电压和延迟，允许Vcc和设置和保持边沿进行测试。

公开(公告)号：US5652531A

公开(公告)日：1997-07-29

申请号：US642335

申请日：1996-05-03

申请人： Ramon S. Co ,  Richard L. Traber

发明人： Ramon S. Co ,  Richard L. Traber

IPC分类号： H03L7/089 ,  H04L7/033 ,  H03K5/22 ,  H03K5/26

CPC分类号： H04L7/033 ,  H03L7/089

摘要： A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.

摘要翻译： 公开了消除锁相环电路中的频率纹波的相位检测器。 检测器包括分别提供UP和DOWN信号的第一和第二电路。 它还包括用于设置DOWN信号的持续时间的延迟元件，以消除相位抖动和静态相位偏移。