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    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LOW RESISTANCE SOURCE-LEVEL CONTACT AND METHOD OF MAKING THEREOF
    52.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LOW RESISTANCE SOURCE-LEVEL CONTACT AND METHOD OF MAKING THEREOF 有权

    公开(公告)号：US20210408031A1

    公开(公告)日：2021-12-30

    申请号：US16910752

    申请日：2020-06-24

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11556

    Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall of each vertical semiconductor channel in the memory opening fill structures. A metal-containing layer is deposited on physically exposed surfaces of the vertical semiconductor channel and the vertical semiconductor channel is crystallized using metal-induced lateral crystallization. Alternatively or additionally, cylindrical metal-semiconductor alloy regions can be formed around the vertical semiconductor channels to reduce contact resistance. A source contact layer can be formed in the source cavity.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING DISCRETE CHARGE STORAGE ELEMENTS AND METHODS OF FORMING THE SAME
    53.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING DISCRETE CHARGE STORAGE ELEMENTS AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210327889A1

    公开(公告)日：2021-10-21

    申请号：US16849600

    申请日：2020-04-15

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Yao-Sheng LEE

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/538 ,  H01L29/423

    Abstract: An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.

    SEMICONDUCTOR STRUCTURE CONTAINING REENTRANT SHAPED BONDING PADS AND METHODS OF FORMING THE SAME
    54.
    发明申请
    SEMICONDUCTOR STRUCTURE CONTAINING REENTRANT SHAPED BONDING PADS AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210296285A1

    公开(公告)日：2021-09-23

    申请号：US16825397

    申请日：2020-03-20

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Senaka KANAKAMEDALA ,  Fei ZHOU

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

    Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

    SEMICONDUCTOR STRUCTURE CONTAINING MULTILAYER BONDING PADS AND METHODS OF FORMING THE SAME
    55.
    发明申请
    SEMICONDUCTOR STRUCTURE CONTAINING MULTILAYER BONDING PADS AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210296269A1

    公开(公告)日：2021-09-23

    申请号：US17118036

    申请日：2020-12-10

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

    IPC: H01L23/00 ,  H01L23/495

    Abstract: A bonded assembly includes a first semiconductor die that includes first semiconductor devices, and a first pad-level dielectric layer and embedding first bonding pads; and a second semiconductor die that includes second semiconductor devices, and a second pad-level dielectric layer embedding second bonding pads that includes a respective second pad base portion. Each of the first bonding pads includes a respective first pad base portion and a respective first metal alloy material portion having a higher coefficient of thermal expansion (CTE) than the respective first pad base portion. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

    CROSS-POINT ARRAY OF FERROELECTRIC FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THE SAME
    57.
    发明申请
    CROSS-POINT ARRAY OF FERROELECTRIC FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20210217775A1

    公开(公告)日：2021-07-15

    申请号：US16738644

    申请日：2020-01-09

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yanli ZHANG ,  Johann ALSMEIER ,  Fei ZHOU

    IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/78 ,  H01L29/66 ,  G11C11/22

    Abstract: A semiconductor structure includes layer stack structures laterally extending along a first horizontal direction and spaced apart from each other along a second horizontal direction by line trenches. Each of the layer stack structures includes at least one instance of a unit layer sequence that includes, from bottom to top or top to bottom, a doped semiconductor source strip, a channel-level insulating strip, and a doped semiconductor drain strip. Line trench fill structures are located within a respective one of the line trenches. Each of the line trench fill structures includes a laterally-alternating sequence of memory pillar structures and dielectric pillar structures. Each of the memory pillar structures includes a gate electrode, at least one pair of ferroelectric dielectric layers, and at least one pair of vertical semiconductor channels located at each level of the channel-level insulating strips.

    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING REPLACEMENT CRYSTALLINE CHANNELS AND METHODS OF MAKING THE SAME
    60.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE INCLUDING REPLACEMENT CRYSTALLINE CHANNELS AND METHODS OF MAKING THE SAME 审中-公开

    公开(公告)号：US20200168619A1

    公开(公告)日：2020-05-28

    申请号：US16200115

    申请日：2018-11-26

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Fei ZHOU ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA

    IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/522

    Abstract: In-process source-level material layers including a source-level sacrificial layer are formed over a substrate. An alternating stack of insulating layers and sacrificial material layers is formed over the in-process source-level material layers. A memory opening is formed through the alternating stack, and is filled with a memory film and a sacrificial opening fill structure. The source-level sacrificial layer is replaced with a source contact layer including a doped polycrystalline semiconductor material. The source contact layer can be formed by diffusing a metal in a metallic catalyst material through a semiconductor fill material layer that fills a source cavity formed by removal of the source-level sacrificial layer. The sacrificial opening fill structure is replaced with a vertical semiconductor channel, which can be formed with large grains due to large crystal sizes in the source contact layer. The sacrificial material layers are replaced with electrically conductive layers.

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