公开(公告)号：US20230269939A1

公开(公告)日：2023-08-24

申请号：US17679335

申请日：2022-02-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Peng ZHANG ,  Yanli ZHANG

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first element, and a second vertical stack of second dielectric oxide material portions located at levels of the electrically conductive layers and including a mixed dielectric oxide material that is a dielectric oxide material of the first element and a second element.

公开(公告)号：US20210358942A1

公开(公告)日：2021-11-18

申请号：US16877328

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Yanli ZHANG

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11543 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.

公开(公告)号：US20210358931A1

公开(公告)日：2021-11-18

申请号：US16876877

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Yanli ZHANG ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Seung-Yeul YANG

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11597 ,  H01L27/11539

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

公开(公告)号：US20210159248A1

公开(公告)日：2021-05-27

申请号：US16694340

申请日：2019-11-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Johann ALSMEIER

IPC: H01L27/11597 ,  G11C11/22 ,  G11C5/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11587 ,  H01L27/1159

Abstract: A ferroelectric field effect transistor (FeFET) includes a semiconductor channel, a source region contacting one end of the semiconductor channel, a drain region contacting a second end of the semiconductor channel, a gate electrode, a ferroelectric gate dielectric layer located between the semiconductor channel and the gate electrode, and a bidirectional selector material layer located between the gate electrode and the ferroelectric gate dielectric layer.

公开(公告)号：US20200303397A1

公开(公告)日：2020-09-24

申请号：US16361722

申请日：2019-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin CUI ,  Kiyohiko SAKAKIBARA ,  Yanli ZHANG

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, drain-select-level trenches that vertically extend through at least one drain-select-level electrically conductive layer and laterally extend along a first horizontal direction and divide each drain-select-level electrically conductive layer into multiple drain-select-level electrically conductive strips, and pairs of vertical conductive strips located within a respective one of the drain-select-level trenches. Each of the vertical conductive strips has a pair of vertical straight sidewalls that laterally extends along the first horizontal direction. Each drain-select-level electrode may have at least one drain-select-level electrically conductive layer and at least one vertical conductive strip.

公开(公告)号：US20200286907A1

公开(公告)日：2020-09-10

申请号：US16882957

申请日：2020-05-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun GE ,  Yanli ZHANG ,  Fei ZHOU ,  Raghuveer S. MAKALA

IPC: H01L27/11568 ,  H01L29/51 ,  H01L29/792 ,  H01L27/1159 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.

公开(公告)号：US20200251149A1

公开(公告)日：2020-08-06

申请号：US16269301

申请日：2019-02-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Zhixin CUI ,  Akio NISHIDA ,  Johann ALSMEIER ,  Yan LI ,  Steven SPROUSE

IPC: G11C5/06 ,  G06F11/08 ,  G11C8/14 ,  H01L25/065 ,  H01L27/105 ,  H01L23/498 ,  H01L23/538

Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.

公开(公告)号：US20190148506A1

公开(公告)日：2019-05-16

申请号：US15813579

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka Krishna KANAKAMEDALA ,  Yoshihiro KANNO ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Jin LIU ,  Murshed CHOWDHURY ,  Yao-Sheng LEE

IPC: H01L29/423 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L29/66 ,  H01L29/49

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

公开(公告)号：US20190035803A1

公开(公告)日：2019-01-31

申请号：US15784549

申请日：2017-10-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Masanori TSUTSUMI ,  Shinsuke YADA ,  Sayako NAGAMINE ,  Johann ALSMEIER

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529

Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.

公开(公告)号：US20230013725A1

公开(公告)日：2023-01-19

申请号：US17933969

申请日：2022-09-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kanta WATANABE ,  Yanli ZHANG

IPC: H01L27/11556 ,  H01L27/11565 ,  H01L27/11524 ,  H01L29/423 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers, a vertical layer stack located over the alternating stack, and including multiple levels of vertically interlaced drain select electrodes and drain-select-level insulating layers, a first insulating layer located between the alternating stack and the vertical layer stack, the first insulating layer having a thickness which is greater than a thickness of the respective insulating layers and the respective drain-select-level insulating layers, drain-select-level isolation structures laterally extending along a first horizontal direction such that drain select electrodes located at a same level are laterally spaced apart from each other by the drain-select-level isolation structures, memory openings vertically extending through the vertical layer stack, the first insulating layer, and the alternating stack, and memory opening fill structures located in the memory openings and including a respective vertical semiconductor channel and a respective memory film.