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公开(公告)号：US20210407603A1
公开(公告)日：2021-12-30
申请号：US16915663
申请日：2020-06-29
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Dengtao Zhao , Huai-Yuan Tseng
Abstract: An apparatus includes a memory controller configured to apply selected one or ones of the program verify voltage levels to a single tier of memory cells. A memory controller is configured to: program data into the plurality of memory cells; and perform a program verify operation across multiple voltage levels with a first voltage level of the program verify operation being applied to a single tier that represents all of the tiers in the memory group and a second voltage level of the program verify operation being applied to multiple tiers, wherein the first voltage level is less than the second voltage level. In embodiments, less than all of the tiers, e.g., two or four tiers, can be used in the program verify to represent all of the tires
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52.发明申请公开(公告)号：US20210405920A1
公开(公告)日：2021-12-30
申请号：US16912381
申请日：2020-06-25
Applicant: SanDisk Technologies LLC
Inventor： Yu-Chung Lien , Mark Murin , Hua-Ling Cynthia Hsu , Tomer Eliash , Huai-Yuan Tseng , Deepanshu Dutta
IPC: G06F3/06 , G11C16/10 , G11C16/32 , H01L25/065
Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.
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公开(公告)号：US11081162B1
公开(公告)日：2021-08-03
申请号：US16798718
申请日：2020-02-24
Applicant: SanDisk Technologies LLC
Inventor： Sarath Puthenthermadam , Yu-Chung Lien , Huai-Yuan Tseng
IPC: G11C16/04 , G11C11/4074 , G11C11/4094 , G11C5/14 , G11C7/14 , G11C5/02 , G11C11/408
Abstract: This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line.
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公开(公告)号：US20210202011A1
公开(公告)日：2021-07-01
申请号：US16729951
申请日：2019-12-30
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Huai-Yuan Tseng , Jiahui Yuan , Dengtao Zhao , Deepanshu Dutta
Abstract: Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate voltages level through the steps. This should reduce energy consumption. The two-page read operation will also reduce the time as the time period to reset the control gates to a low state are not required in between the page read operations.
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公开(公告)号：US20210134369A1
公开(公告)日：2021-05-06
申请号：US16668675
申请日：2019-10-30
Applicant: SanDisk Technologies LLC
Inventor： Zhiping Zhang , Muhammad Masuduzzaman , Huai-Yuan Tseng , Dengtao Zhao , Deepanshu Dutta
IPC: G11C16/10 , G11C16/24 , G11C11/4074 , G11C11/409
Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the fist memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.
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Patent Agency Ranking
公开(公告)号：US20200258571A1
公开(公告)日：2020-08-13
申请号：US16829888
申请日：2020-03-25
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Huai-Yuan Tseng , Deepanshu Dutta
Abstract: Apparatuses, systems, and methods are disclosed for adjusting a programming setting such as a programming voltage of a set of non-volatile storage cells, such as an SLC NAND array. The non-volatile storage cells may be arranged into a plurality of word lines. A subset of the non-volatile storage cells may be configured to store a programming setting. An on-die controller may be configured to read the programming setting from the setting subset, and write data to the non-volatile storage cells, using the programming setting. The on-die controller may further be configured to determine that the programming setting causes suboptimal programming of one or more of the non-volatile storage cells, and in response to the determination, store a revised programming setting on the setting subset.
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公开(公告)号：US20200243138A1
公开(公告)日：2020-07-30
申请号：US16842112
申请日：2020-04-07
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Huai-Yuan Tseng , Deepanshu Dutta
Abstract: Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.
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公开(公告)号：US10468111B1
公开(公告)日：2019-11-05
申请号：US15967270
申请日：2018-04-30
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Huai-Yuan Tseng , Deepanshu Dutta
Abstract: Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.
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公开(公告)号：US20190333588A1
公开(公告)日：2019-10-31
申请号：US15967270
申请日：2018-04-30
Applicant: SanDisk Technologies LLC
Inventor： Xiang YANG , Huai-Yuan Tseng , Deepanshu Dutta
Abstract: Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.
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公开(公告)号：US20190318792A1
公开(公告)日：2019-10-17
申请号：US15952752
申请日：2018-04-13
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Huai-Yuan Tseng , Deepanshu Dutta
IPC: G11C16/34 , G11C16/10 , G11C16/26 , G11C16/04 , H01L27/11556 , H01L27/11582
Abstract: Apparatuses and techniques are described for optimizing a program operation in a memory device. A storage location stores programing data for each word line, such as a program voltage for a set of memory cells. The set of memory cells may be periodically evaluated to determine updated programming setting(s). In one approach, the evaluation involves repeatedly sensing the set of memory cells between a program pulse and a verify signal in a program loop. The word line voltage can be stepped down to an intermediate voltage, then ramped down at a controlled rate while repeatedly sensing the memory cells, such as to detect an upper or lower tail of a threshold voltage distribution. The position of the tail can indicate a degree of over programming and this information can be used to adjust the programming setting(s) in a subsequent program operation.
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