公开(公告)号：US08742969B2

公开(公告)日：2014-06-03

申请号：US13323527

申请日：2011-12-12

申请人： Kenneth Thet Zin Oo ,  Pierte Roo ,  Xiong Liu

发明人： Kenneth Thet Zin Oo ,  Pierte Roo ,  Xiong Liu

IPC分类号： H03M1/14

CPC分类号： H03M1/14 ,  H03M1/06 ,  H03M1/1014 ,  H03M1/124 ,  H03M1/167 ,  H03M1/36

摘要： First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. The coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the coarse references and outputs a coarse output based on the first comparison. A switch matrix includes switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides fine references. A fine ADC performs a second comparison of the input voltage and the fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.

摘要翻译： 第一和第二跟踪和保持级跟踪并存储模拟输入信号的采样的输入电压。 粗略参考梯形图提供多个粗略参考。 粗略参考梯形图包括第一粗略参考和第二粗略参考梯形图。 粗略的ADC执行输入电压和粗略参考的第一次比较，并输出基于第一次比较的粗略输出。 开关矩阵包括开关，并且被配置为基于粗略输出闭合对应于粗略参考的开关。 一个精细的参考梯子提供了很好的参考。 精细ADC对输入电压和精细基准进行第二次比较，并根据第二次比较输出精细输出。 逻辑输出基于粗略输出和精细输出的模拟输入信号采样的数字输出。

公开(公告)号：US08170167B1

公开(公告)日：2012-05-01

申请号：US13042344

申请日：2011-03-07

申请人： Pierte Roo

发明人： Pierte Roo

IPC分类号： H04L7/04

CPC分类号： H04L7/0033 ,  H03D3/248 ,  H04L7/0337

摘要： A communication system including a plurality of communication devices configured to operate according to a plurality of communication clock signals, respectively, wherein the plurality of communication clock signals are based on a common reference clock signal. The communication system further includes a phase-locked loop configured to generate an output signal in response to the common reference clock signal, wherein the output signal is in phase lock with the common reference clock signal; a signal division controller configured to generate a divider reset signal in response to a binary select signal; and a divider configured to generate one of the plurality of communication clock signals by performing frequency division of the output signal, wherein the divider reset signal controls a start time of the frequency division.

摘要翻译： 一种通信系统，包括多个通信设备，其被配置为分别根据多个通信时钟信号进行操作，其中所述多个通信时钟信号基于公共参考时钟信号。 通信系统还包括锁相环，配置为响应于公共参考时钟信号产生输出信号，其中输出信号与公共参考时钟信号同相锁定; 信号分配控制器，被配置为响应于二进制选择信号产生分频器复位信号; 以及分配器，其被配置为通过执行所述输出信号的分频来生成所述多个通信时钟信号中的一个，其中所述分频器复位信号控制所述分频的开始时间。

公开(公告)号：US08077069B2

公开(公告)日：2011-12-13

申请号：US12684735

申请日：2010-01-08

申请人： Kenneth Thet Zin Oo ,  Pierte Roo ,  Xiong Liu

发明人： Kenneth Thet Zin Oo ,  Pierte Roo ,  Xiong Liu

IPC分类号： H03M1/14

CPC分类号： H03M1/14 ,  H03M1/06 ,  H03M1/1014 ,  H03M1/124 ,  H03M1/167 ,  H03M1/36

摘要： First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. In one embodiment, the coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the plurality of coarse references and outputs a coarse output based on the first comparison. A switch matrix includes a plurality of switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides a plurality of fine references. A fine ADC performs a second comparison of the input voltage and the plurality of fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.

摘要翻译： 第一和第二跟踪和保持级跟踪并存储模拟输入信号的采样的输入电压。 粗略参考梯形图提供多个粗略参考。 在一个实施例中，粗略参考梯形图包括第一粗略参考和第二粗略参考梯形图。 粗略ADC执行输入电压和多个粗略参考的第一比较，并且基于第一比较输出粗略输出。 开关矩阵包括多个开关，并且被配置为基于粗略输出闭合对应于粗略参考的开关。 精细的参考梯子提供多个精细参考。 精细ADC执行输入电压和多个精细基准的第二比较，并且基于第二比较输出精细输出。 逻辑输出基于粗略输出和精细输出的模拟输入信号采样的数字输出。

公开(公告)号：US07564900B1

公开(公告)日：2009-07-21

申请号：US12287077

申请日：2008-10-06

申请人： Pierte Roo

发明人： Pierte Roo

IPC分类号： H03H7/30 ,  H03K5/159

CPC分类号： H04L25/03057 ,  H04L2025/03503 ,  H04L2025/03605

摘要： A mixed-mode signal processor includes a first summer having a first input that receives a first analog signal, a second input and an output that supplies a second analog signal. A decision circuit outputs a digital signal based on the second analog signal. A mixed-mode decision feedback equalizer (DFE) includes a plurality of tap weights and outputs a DFE signal to the second input of the summer based on the first analog signal, the digital signal and the plurality of tap weights.

摘要翻译： 混合模式信号处理器包括具有接收第一模拟信号的第一输入的第一加法器，提供第二模拟信号的第二输入和输出。 决定电路基于第二模拟信号输出数字信号。 混合模式判决反馈均衡器（DFE）包括多个抽头权重，并且基于第一模拟信号，数字信号和多个抽头权重将DFE信号输出到加法器的第二输入。

公开(公告)号：US07433665B1

公开(公告)日：2008-10-07

申请号：US09920241

申请日：2001-08-01

申请人： Pierte Roo

发明人： Pierte Roo

IPC分类号： H04B1/10 ,  H04B3/20 ,  H04B1/38

CPC分类号： H04B1/581 ,  H04L25/0272

摘要： A communication circuit for an Ethernet or other network transceiver includes a first sub-circuit having a first input which receives a composite differential signal including first and second differential signal components, a second input which receives a differential replica transmission signal, and an output which provides a differential receive signal which comprises the composite differential signal minus the differential replica transmission signal. The communication circuit also includes a second sub-circuit which produces first and second single-ended replica transmission signals which together substantially comprise a replica of the first differential signal component of the composite differential signal and a third sub-circuit, which is coupled to the first and second sub-circuits, and which produces the differential replica transmission signal from the first and second single-ended replica transmission signals.

摘要翻译： 用于以太网或其它网络收发器的通信电路包括具有第一输入的第一子电路，其接收包括第一和第二差分信号分量的复合差分信号，接收差分复制传输信号的第二输入端和提供 差分接收信号，其包括复合差分信号减去差分复制传输信号。 通信电路还包括产生第一和第二单端复制传输信号的第二子电路，其一起基本上包括复合差分信号的第一差分信号分量的副本和第三子电路，第三子电路耦合到 第一和第二子电路，并且从第一和第二单端副本传输信号产生差分复制传输信号。

公开(公告)号：US07433401B1

公开(公告)日：2008-10-07

申请号：US10443972

申请日：2003-05-22

申请人： Pierte Roo

发明人： Pierte Roo

IPC分类号： H03H7/30 ,  H03K5/159

CPC分类号： H04L25/03057 ,  H04L2025/03503 ,  H04L2025/03605

摘要： A mixed-mode signal processor architecture provides decision feedback equalization for a communications channel. A decision circuit compares an analog signal to a predetermined threshold and outputs a digital signal based on the comparison. A mixed-mode decision feedback equalizer (DFE) includes a plurality of tap weights and produces a DFE signal using the analog signal, the digital signal, and the tap weights. A first summer has a first input that communicates with an input of the decision circuit, a second input that communicates with an output of the decision circuit, and an output. An adaptation circuit communicates with the output of the first summer and adjusts the tap weights of the mixed-mode DFE, the clock signal a timing of the clock signal of a PLL, and an automatic gain control signal of an amplifier.

摘要翻译： 混合模式信号处理器架构为通信信道提供判决反馈均衡。 判定电路将模拟信号与预定阈值进行比较，并根据比较输出数字信号。 混合模式判决反馈均衡器（DFE）包括多个抽头权重并且使用模拟信号，数字信号和抽头权重产生DFE信号。 第一夏天具有与判定电路的输入通信的第一输入端，与判定电路的输出通信的第二输入端和输出端。 适应电路与第一个加法器的输出进行通信，调整混合模式DFE的抽头权重，时钟信号，PLL的时钟信号的定时和放大器的自动增益控制信号。

公开(公告)号：US07358876B1

公开(公告)日：2008-04-15

申请号：US11505513

申请日：2006-08-16

申请人： Kenneth Thet Zin Oo ,  Olakanmi Oluwole ,  Pierte Roo

发明人： Kenneth Thet Zin Oo ,  Olakanmi Oluwole ,  Pierte Roo

IPC分类号： H03M1/06

CPC分类号： H03M1/0607 ,  H03M1/12

摘要： A circuit includes a chopper switch to receive an analog input signal and output a first chopped signal of a first polarity during a first clock phase and a second chopped signal of a second polarity during a second clock phase. An analog block receives and processes the first and second chopped signals and outputs first and second processed signals, respectively. The analog bock has a first offset voltage associated thereto. The first and second processed signals, each includes a first offset component that is associated with the first offset voltage. A data converter receives and converts the first and second processed signals into first and second digital codes, respectively. An offset canceller receives the first and second digital codes. The offset canceller is configured to remove the first offset components from the first and second digital codes and output a digital output signal corresponding to the analog input signal.

摘要翻译： 电路包括斩波开关，以在第二时钟相位期间在第一时钟相位期间接收模拟输入信号并输出​​第一极性的第一斩波信号和第二极性的第二斩波信号。 模拟块接收并处理第一和第二斩波信号并分别输出第一和第二处理信号。 模拟块具有与其相关联的第一偏移电压。 第一和第二处理信号各自包括与第一偏移电压相关联的第一偏移分量。 数据转换器分别接收第一和第二处理信号并转换成第一和第二数字代码。 偏移消除器接收第一和第二数字码。 偏移消除器被配置为从第一和第二数字代码中去除第一偏移分量，并输出与模拟输入信号对应的数字输出信号。

公开(公告)号：US07327995B1

公开(公告)日：2008-02-05

申请号：US11523169

申请日：2006-09-19

申请人： Pierte Roo

发明人： Pierte Roo

IPC分类号： H04B1/10 ,  H04B3/20 ,  H04B1/38

CPC分类号： H04B1/581 ,  H04B3/23 ,  H04B3/32

摘要： A transmit canceller comprises an operational amplifier having a first polarity input terminal, a second polarity input terminal, and an output terminal. A feedback element communicates with the second polarity input terminal and the output terminal. A first input resistor communicates with the second polarity input terminal and the measured signal input. A second input resistor communicates with the second polarity input terminal and the replica signal input. A predetermined voltage source communicates with the first polarity input terminal of the operational amplifier. The received signal is an output at the output terminal of the operational amplifier.

摘要翻译： 发射消除器包括具有第一极性输入端，第二极性输入端和输出端的运算放大器。 反馈元件与第二极性输入端子和输出端子通信。 第一输入电阻与第二极性输入端和测量信号输入进行通信。 第二输入电阻器与第二极性输入端子和副本信号输入端相通。 预定的电压源与运算放大器的第一极性输入端通信。 接收信号是运算放大器的输出端的输出。

公开(公告)号：US06459246B1

公开(公告)日：2002-10-01

申请号：US09880599

申请日：2001-06-13

申请人： Pierte Roo

发明人： Pierte Roo

IPC分类号： G05F140

CPC分类号： G05F1/575

摘要： A linear voltage regulator generates a regulated output voltage from a low overhead input voltage. The voltage regulator includes a series pass device that generates the output voltage based on a control signal. A sense circuit generates a sense signal that is proportional to the output voltage. An integrator generates an integrated signal based on a difference between a first voltage reference and the sense signal. The integrated signal includes a first voltage reference component and a sense signal component. A summer generates the control signal in response to the integrated signal, a second voltage reference, and the sense signal. The first voltage reference component of the integrated signal has the opposite polarity of the second voltage reference and the sense signal component of the integrated signal is of the same polarity as the sense signal.

摘要翻译： 线性稳压器从低开销输入电压产生稳压输出电压。 电压调节器包括基于控制信号产生输出电压的串联装置。 感测电路产生与输出电压成正比的感测信号。 积分器基于第一电压基准和感测信号之间的差产生积分信号。 集成信号包括第一电压参考分量和感测信号分量。 夏天响应于积分信号，第二参考电压和感测信号产生控制信号。 积分信号的第一参考分量具有与第二参考电压相反的极性，并且积分信号的感测信号分量具有与感测信号相同的极性。