公开(公告)号：US06888843B2

公开(公告)日：2005-05-03

申请号：US09398624

申请日：1999-09-17

申请人： James B. Keller ,  Derrick R. Meyer

发明人： James B. Keller ,  Derrick R. Meyer

IPC分类号： G06F13/40 ,  H04L12/54

CPC分类号： G06F13/405

摘要： A computer system employs virtual channels and allocates different resources to the virtual channels. Packets which do not have logical/protocol-related conflicts are grouped into a virtual channel. Accordingly, logical conflicts occur between packets in separate virtual channels. The packets within a virtual channel may share resources (and hence experience resource conflicts), but the packets within different virtual channels may not share resources. Since packets which may experience resource conflicts do not experience logical conflicts, and since packets which may experience logical conflicts do not experience resource conflicts, deadlock-free operation may be achieved. Additionally, nodes within the computer system may be configured to preallocate resources to process response packets. Some response packets may have logical conflicts with other response packets, and hence would normally not be allocable to the same virtual channel. However, by preallocating response-processing resources, response packets are accepted by the destination node. Thus, any resource conflicts which may occur are temporary (as the response packets which make forward progress are processable). Viewed in another way, response packets may be logically independent if the destination node is capable of processing the response packets upon receipt. Accordingly, a response virtual channel is formed to which each response packet belongs.

摘要翻译： 计算机系统采用虚拟通道并为虚拟通道分配不同的资源。 没有逻辑/协议相关冲突的数据包被分组成虚拟通道。 因此，在分离的虚拟通道中的分组之间发生逻辑冲突。 虚拟通道内的数据包可能共享资源（从而遇到资源冲突），但不同虚拟通道内的数据包可能不共享资源。 由于可能遇到资源冲突的数据包不会出现逻辑冲突，并且由于可能遇到逻辑冲突的数据包不会遇到资源冲突，因此可能会实现无死锁操作。 此外，计算机系统内的节点可以被配置为预先分配资源以处理响应分组。 一些响应分组可能与其他响应分组具有逻辑冲突，因此通常不能分配给相同的虚拟信道。 然而，通过预分配响应处理资源，响应分组被目的节点接受。 因此，可能发生的任何资源冲突都是临时的（因为可以进行进展的响应数据包是可处理的）。 以另一种方式观察，如果目的地节点在接收时能够处理响应分组，则响应分组可以在逻辑上是独立的。 因此，形成每个响应分组所属的响应虚拟信道。

公开(公告)号：US06877076B1

公开(公告)日：2005-04-05

申请号：US10626790

申请日：2003-07-24

申请人： James Y. Cho ,  James B. Keller ,  Mark D. Hayter

发明人： James Y. Cho ,  James B. Keller ,  Mark D. Hayter

IPC分类号： G06F12/02 ,  G06F12/06

CPC分类号： G06F12/0653 ,  G06F12/0215 ,  G06F12/0607

摘要： A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized for a given application by programming the configuration registers. For example, in one embodiment, the portion of the address of a memory transaction used to select a storage location for access in response to the memory transaction may be programmable. In an implementation designed for DRAM, a first portion may be programmably selected to form the row address and a second portion may be programmable selected to form the column address. Additional embodiments may further include programmable selection of the portion of the address used to select a bank. Still further, interleave modes among memory sections assigned to different chip selects and among two or more channels to memory may be programmable, in some implementations. Furthermore, the portion of the address used to select between interleaved memory sections or interleaved channels may be programmable. One particular implementation may include all of the above programmable features, which may provide a high degree of flexibility in optimizing the memory system.

摘要翻译： 存储器控制器通过一个或多个配置寄存器为存储器的配置提供可编程的灵活性。 可以通过编程配置寄存器来为给定应用优化存储器。 例如，在一个实施例中，用于响应于存储器事务选择用于访问的存储位置的存储器事务的地址部分可以是可编程的。 在为DRAM设计的实现中，可编程地选择第一部分以形成行地址，并且第二部分可以被编程选择以形成列地址。 另外的实施例还可以包括用于选择银行的地址部分的可编程选择。 此外，在一些实现中，分配给不同芯片选择的存储器部分之间的交织模式和在存储器的两个或更多个通道中的交织模式可以是可编程的。 此外，用于在交织的存储器部分或交织的信道之间选择的地址的部分可以是可编程的。 一个具体实现可以包括所有上述可编程特征，其可以在优化存储器系统时提供高度的灵活性。

公开(公告)号：US06721813B2

公开(公告)日：2004-04-13

申请号：US09774148

申请日：2001-01-30

申请人： Jonathan M. Owen ,  Mark D. Hummel ,  James B. Keller

发明人： Jonathan M. Owen ,  Mark D. Hummel ,  James B. Keller

IPC分类号： G06F1300

CPC分类号： G06F13/4243

摘要： A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem and an input/output (I/O) subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor preferably executing software instructions. The I/O subsystem includes one or more I/O nodes. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The multiple processing nodes may include a first processing node and a second processing node, wherein the first processing node includes a host bridge, and wherein a memory is coupled to the second processing node. An I/O node may generate a non-coherent write transaction to store data within the second processing node's memory, wherein the non-coherent write transaction is a posted write transaction. The I/O node may dispatch the non-coherent write transaction directed to the host bridge. The host bridge may respond to the non-coherent write transaction by translating the non-coherent write transaction to a coherent write transaction, and dispatching the coherent write transaction to the second processing node. The second processing node may respond to the coherent write transaction by dispatching a target done response directed to the host bridge.

摘要翻译： 提出了一种实现用于跟踪已发布的写入事务进度的系统和方法的计算机系统。 在一个实施例中，计算机系统包括处理子系统和输入/输出（I / O）子系统。 处理子系统包括通过相干通信链路互连的多个处理节点。 每个处理节点可以包括优选执行软件指令的处理器。 I / O子系统包括一个或多个I / O节点。 每个I / O节点可以体现一个或多个I / O功能（例如，调制解调器，声卡等）。 多个处理节点可以包括第一处理节点和第二处理节点，其中第一处理节点包括主机桥，并且其中存储器耦合到第二处理节点。 I / O节点可以生成非相干写事务以在第二处理节点的存储器内存储数据，其中非相干写事务是已发布的写事务。 I / O节点可以调度定向到主桥的非相干写入事务。 主桥可以通过将非相干写事务转换为相干写事务来响应非相干写事务，并将相干写事务分派到第二处理节点。 第二处理节点可以通过调度定向到主桥的目标完成响应来响应相干写事务。

公开(公告)号：US06694424B1

公开(公告)日：2004-02-17

申请号：US09476579

申请日：2000-01-03

申请人： James B. Keller ,  Thomas S. Green ,  Wei-Han Lien ,  Ramsey W. Haddad

发明人： James B. Keller ,  Thomas S. Green ,  Wei-Han Lien ,  Ramsey W. Haddad

IPC分类号： G06F900

CPC分类号： G06F9/3855 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3859

摘要： A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e.g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC. A second table maintains a corresponding portion of the store PCs of recently dispatched stores, along with tags identifying the recently dispatched stores. In another implementation, the STLF predictor records a difference between the tags assigned to a load and a store which interferes with the load in a first table indexed by the load PC. The PC of the dispatching load is used to select a difference from the table, and the difference is added to the tag assigned to the load.

摘要翻译： 处理器使用存储来加载（STLF）预测器，其可以指示用于调度负载对存储的依赖性。 对于在先前执行期间干扰负载的执行的存储器，指示依赖性。 由于在存储器上指示依赖关系，所以在存储之前防止了负载的调度和/或执行。 响应于执行负载并存储和检测干扰，STLF预测器被训练用于特定负载和存储的信息。 此外，如果由STLF预测器指示负载依赖于特定存储并且实际上不发生依赖性，则STLF预测器可以是未经训练的（例如，针对特定负载的信息可以被删除）。 在一个实现中，STLF预测器在由负载PC索引的第一表中记录干扰负载的商店的PC的至少一部分。 第二个表维护最近派驻的商店的商店PC的相应部分，以及标识最近派发的商店的标签。 在另一实现中，STLF预测器记录分配给负载的标签与由负载PC索引的第一表中的负载干扰的存储器之间的差异。 调度负载的PC用于选择与表的差异，并将差值添加到分配给负载的标签。

公开(公告)号：US06687789B1

公开(公告)日：2004-02-03

申请号：US09476577

申请日：2000-01-03

申请人： James B. Keller ,  Keith R. Schakel ,  Puneet Sharma

发明人： James B. Keller ,  Keith R. Schakel ,  Puneet Sharma

IPC分类号： G06F1200

CPC分类号： G06F12/0864 ,  G06F9/30149 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F2212/6082 ,  Y02D10/13

摘要： A cache is coupled to receive an input address and a corresponding way prediction. The cache provides output bytes in response to the predicted way (instead of, performing tag comparisons to select the output bytes). Furthermore, a tag may be read from the predicted way and only partial tags are read from the non-predicted ways. The tag is compared to the tag portion of the input address, and the partial tags are compared to a corresponding partial tag portion of the input address. If the tag matches the tag portion of the input address, a hit in the predicted way is detected and the bytes provided in response to the predicted way are correct. If the tag does not match the tag portion of the input address, a miss in the predicted way is detected. If none of the partial tags match the corresponding partial tag portion of the input address, a miss in the cache is determined. On the other hand, if one or more of the partial tags match the corresponding partial tags portion of the input address, the cache searches the corresponding ways to determine whether or not the input address hits or misses in the cache.

摘要翻译： 高速缓存被耦合以接收输入地址和相应的方式预测。 缓存提供响应于预测方式的输出字节（而不是执行标签比较以选择输出字节）。 此外，可以从预测的方式读取标签，并且仅从非预测方式读取部分标签。 将标签与输入地址的标签部分进行比较，并将部分标签与输入地址的相应部分标签部分进行比较。 如果标签与输入地址的标签部分匹配，则以预测的方式检测到命中，并且响应于预测方式提供的字节是正确的。 如果标签与输入地址的标签部分不匹配，则以预测的方式检测到未命中。 如果部分标签中没有一个与输入地址的相应部分标签部分匹配，则确定高速缓存中的未命中。 另一方面，如果一个或多个部分标签与输入地址的相应部分标签部分匹配，则高速缓存搜索相应的方式以确定输入地址是否在高速缓存中命中或丢失。

公开(公告)号：US06625685B1

公开(公告)日：2003-09-23

申请号：US09665989

申请日：2000-09-20

申请人： James Y. Cho ,  James B. Keller ,  Mark D. Hayter

发明人： James Y. Cho ,  James B. Keller ,  Mark D. Hayter

IPC分类号： G06F1200

CPC分类号： G06F12/0653 ,  G06F12/0215 ,  G06F12/0607

摘要： A memory controller provides programmable flexibility, via one or more configuration registers, for the configuration of the memory. The memory may be optimized for a given application by programming the configuration registers. For example, in one embodiment, the portion of the address of a memory transaction used to select a storage location for access in response to the memory transaction may be programmable. In an implementation designed for DRAM, a first portion may be programmably selected to form the row address and a second portion may be programmable selected to form the column address. Additional embodiments may further include programmable selection of the portion of the address used to select a bank. Still further, interleave modes among memory sections assigned to different chip selects and among two or more channels to memory may be programmable, in some implementations. Furthermore, the portion of the address used to select between interleaved memory sections or interleaved channels may be programmable. One particular implementation may include all of the above programmable features, which may provide a high degree of flexibility in optimizing the memory system.

摘要翻译： 存储器控制器通过一个或多个配置寄存器为存储器的配置提供可编程的灵活性。 可以通过编程配置寄存器来为给定应用优化存储器。 例如，在一个实施例中，用于响应于存储器事务选择用于访问的存储位置的存储器事务的地址部分可以是可编程的。 在为DRAM设计的实现中，可编程地选择第一部分以形成行地址，并且第二部分可以被编程选择以形成列地址。 另外的实施例还可以包括用于选择银行的地址部分的可编程选择。 此外，在一些实现中，分配给不同芯片选择的存储器部分之间的交织模式和在存储器的两个或更多个通道中的交织模式可以是可编程的。 此外，用于在交织的存储器部分或交织的信道之间选择的地址的部分可以是可编程的。 一个具体实现可以包括所有上述可编程特征，其可以在优化存储器系统时提供高度的灵活性。

公开(公告)号：US06560694B1

公开(公告)日：2003-05-06

申请号：US09483755

申请日：2000-01-14

申请人： Kevin J. McGrath ,  James B. Keller

发明人： Kevin J. McGrath ,  James B. Keller

IPC分类号： G06F9355

CPC分类号： G06F9/30189 ,  G06F9/30185 ,  G06F9/342

摘要： A processor supports an operating mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the operating mode. The operating mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Additionally, a first instruction prefix may be coded into an instruction to override the default operand size to a first non-default operand size (e.g. 64 bits). Furthermore, a second instruction prefix may be coded into an instruction in addition to the first instruction prefix to override the default operand size to a second non-default operand size (e.g. 16 bits). Thus operand sizes of 64, 32, and 16 bits may be used when desired.

摘要翻译： 处理器支持默认地址大小大于32位，默认操作数大小为32位的操作模式。 尽管处理器的各种实施例可以在操作模式下实现超过32位，高达并包括64位的任何地址大小，但默认地址大小可以名义上表示为64位。 可以通过将控制寄存器中的使能指示置于使能状态并且通过将段描述符中的第一操作模式指示和第二操作模式指示设置为预定义状态来建立操作模式。 此外，第一指令前缀可以被编码到用于将默认操作数大小重写为第一非默认操作数大小（例如，64位）的指令。 此外，除了第一指令前缀之外，还可以将第二指令前缀编码为指令，以将默认操作数大小覆盖到第二非默认操作数大小（例如16位）。 因此，当需要时可以使用64位，32位和16位的操作数大小。

公开(公告)号：US06546478B1

公开(公告)日：2003-04-08

申请号：US09418098

申请日：1999-10-14

申请人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

发明人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

IPC分类号： G06F938

CPC分类号： G06F9/3816 ,  G06F9/30149 ,  G06F9/322 ,  G06F9/3804 ,  G06F9/384

摘要： A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch address, as well as one or more additional instructions subsequent to that instruction. The alignment information may be, for example, instruction pointers, each of which directly locates a corresponding instruction within a plurality of instruction bytes fetched in response to the fetch address. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Furthermore, each entry may store additional information regarding the terminating instruction within the entry. In one embodiment, the additional information includes an indication of the branch displacement when the terminating instruction is a branch instruction. In another embodiment, the additional information includes the entry point for a microcode instruction when the terminating instruction is a microcode instruction. Furthermore, the microcode instruction may be identified by an instruction pointer corresponding to a particular decode unit which is coupled to the microcode unit.

摘要翻译： 行预测器缓存对齐信息的指令。 响应于每个提取地址，行预测器提供从取指址开始的指令的对齐信息，以及该指令之后的一个或多个附加指令。 对准信息可以是例如指令指针，每个指令指针直接定位响应于取出地址取出的多个指令字节中的对应指令。 线预测器可以包括具有多个条目的存储器，每个条目存储多达预定义的最大数量的指令指针以及与由指令指针中的第一个标识的指令相对应的读取地址。 此外，每个条目可以存储关于条目内的终止指令的附加信息。 在一个实施例中，附加信息包括当终止指令是分支指令时分支位移的指示。 在另一个实施例中，当终止指令是微码指令时，附加信息包括微代码指令的入口点。 此外，微代码指令可以由对应于耦合到微代码单元的特定解码单元的指令指针来识别。

公开(公告)号：US06502185B1

公开(公告)日：2002-12-31

申请号：US09476936

申请日：2000-01-03

申请人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

发明人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

IPC分类号： G06F930

CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/3861

摘要： A processor includes an instruction cache and a predecode cache which is not actively maintained coherent with the instruction cache. The processor fetches instruction bytes from the instruction cache and predecode information from the predecode cache. Instructions are provided to a plurality of decode units based on the predecode information, and the decode units decode the instructions and verify that the predecode information corresponds to the instructions. More particularly, each decode unit may verify that a valid instruction was decoded, and that the instruction succeeds a preceding instruction decoded by another decode unit. Additionally, other units involved in the instruction processing pipeline stages prior to decode may verify portions of the predecode information. If the predecode information does not correspond to the fetched instructions, the predecode information may be corrected (either by predecoding the instruction bytes or by updating the predecode information, if the update may be determined without predecoding the instruction bytes). In one particular embodiment, the predecode cache may be a line predictor which stores instruction pointers indexed by a portion of the fetch address. The line predictor may thus experience address aliasing, and predecode information may therefore not correspond to the instruction bytes. However, power may be conserved by not storing and comparing the entire fetch address.

摘要翻译： 处理器包括指令高速缓存和未被主动地保持与指令高速缓存相关联的预解码高速缓存。 处理器从指令高速缓存中获取指令字节，并从预代码高速缓存预先解码信息。 基于预解码信息向多个解码单元提供指令，并且解码单元解码指令并验证预解码信息对应于指令。 更具体地，每个解码单元可以验证有效指令被解码，并且该指令成功接收由另一解码单元解码的先前指令。 此外，涉及在解码之前的指令处理流水线阶段的其他单元可以验证预解码信息的部分。 如果预解码信息不对应于获取的指令，则可以通过预编码指令字节或通过更新预解码信息来校正预解码信息，如果可以在不预编译指令字节的情况下确定更新的话）。 在一个特定实施例中，预解码高速缓存可以是存储由获取地址的一部分索引的指令指针的行预测器。 因此，线预测器可能会遇到地址混叠，因此预解码信息可能不对应于指令字节。 然而，通过不存储和比较整个读取地址可以节省功率。

公开(公告)号：US06385705B1

公开(公告)日：2002-05-07

申请号：US09702147

申请日：2000-10-30

申请人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

发明人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

IPC分类号： G06F1300

CPC分类号： G06F13/1621

摘要： A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.