公开(公告)号：US06647490B2

公开(公告)日：2003-11-11

申请号：US09419832

申请日：1999-10-14

申请人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

发明人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

IPC分类号： G06F938

CPC分类号： G06F9/30149 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/3808 ,  G06F9/3816 ,  G06F9/382

摘要： A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch address, as well as one or more additional instructions subsequent to that instruction. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Additionally, each entry may include a link to another entry storing instruction pointers to the next instructions within the predicted instruction stream, and a next fetch address corresponding to the first instruction within the next entry. The next fetch address may be provided to the instruction cache to fetch the corresponding instruction bytes. If the terminating instruction within the entry is a branch instruction, the line predictor is trained with respect to the next fetch address (and next index within the line predictor, which provides the link to the next entry). As line predictor entries are created, a set of branch predictors may be accessed to provide an initial next fetch address and index. The initial training is verified by accessing the branch predictors at each fetch of the line predictor entry, and updated as dictated by the state of the branch predictors at each fetch.

摘要翻译： 行预测器缓存对齐信息的指令。 响应于每个提取地址，行预测器提供从取指址开始的指令的对齐信息，以及该指令之后的一个或多个附加指令。 线预测器可以包括具有多个条目的存储器，每个条目存储多达预定义的最大数量的指令指针以及与由指令指针中的第一个标识的指令相对应的读取地址。 此外，每个条目可以包括链接到存储指向预测指令流中的下一个指令的指令的另一个条目，以及对应于下一条目中的第一指令的下一个提取地址。 可以将下一个提取地址提供给指令高速缓存以获取对应的指令字节。 如果条目中的终止指令是分支指令，则线路预测器相对于下一个提取地址（以及行预测器中的下一个索引（其提供到下一个条目的链接））进行训练。 当创建线预测值条目时，可以访问一组分支预测器来提供初始的下一个提取地址和索引。 通过在行预测器条目的每次获取时访问分支预测器来验证初始训练，并且根据每次获取时分支预测器的状态来更新初始训练。

公开(公告)号：US06546478B1

公开(公告)日：2003-04-08

申请号：US09418098

申请日：1999-10-14

申请人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

发明人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

IPC分类号： G06F938

CPC分类号： G06F9/3816 ,  G06F9/30149 ,  G06F9/322 ,  G06F9/3804 ,  G06F9/384

摘要： A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides alignment information for the instruction beginning at the fetch address, as well as one or more additional instructions subsequent to that instruction. The alignment information may be, for example, instruction pointers, each of which directly locates a corresponding instruction within a plurality of instruction bytes fetched in response to the fetch address. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Furthermore, each entry may store additional information regarding the terminating instruction within the entry. In one embodiment, the additional information includes an indication of the branch displacement when the terminating instruction is a branch instruction. In another embodiment, the additional information includes the entry point for a microcode instruction when the terminating instruction is a microcode instruction. Furthermore, the microcode instruction may be identified by an instruction pointer corresponding to a particular decode unit which is coupled to the microcode unit.

摘要翻译： 行预测器缓存对齐信息的指令。 响应于每个提取地址，行预测器提供从取指址开始的指令的对齐信息，以及该指令之后的一个或多个附加指令。 对准信息可以是例如指令指针，每个指令指针直接定位响应于取出地址取出的多个指令字节中的对应指令。 线预测器可以包括具有多个条目的存储器，每个条目存储多达预定义的最大数量的指令指针以及与由指令指针中的第一个标识的指令相对应的读取地址。 此外，每个条目可以存储关于条目内的终止指令的附加信息。 在一个实施例中，附加信息包括当终止指令是分支指令时分支位移的指示。 在另一个实施例中，当终止指令是微码指令时，附加信息包括微代码指令的入口点。 此外，微代码指令可以由对应于耦合到微代码单元的特定解码单元的指令指针来识别。

公开(公告)号：US06502185B1

公开(公告)日：2002-12-31

申请号：US09476936

申请日：2000-01-03

申请人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

发明人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

IPC分类号： G06F930

CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/322 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/3861

摘要： A processor includes an instruction cache and a predecode cache which is not actively maintained coherent with the instruction cache. The processor fetches instruction bytes from the instruction cache and predecode information from the predecode cache. Instructions are provided to a plurality of decode units based on the predecode information, and the decode units decode the instructions and verify that the predecode information corresponds to the instructions. More particularly, each decode unit may verify that a valid instruction was decoded, and that the instruction succeeds a preceding instruction decoded by another decode unit. Additionally, other units involved in the instruction processing pipeline stages prior to decode may verify portions of the predecode information. If the predecode information does not correspond to the fetched instructions, the predecode information may be corrected (either by predecoding the instruction bytes or by updating the predecode information, if the update may be determined without predecoding the instruction bytes). In one particular embodiment, the predecode cache may be a line predictor which stores instruction pointers indexed by a portion of the fetch address. The line predictor may thus experience address aliasing, and predecode information may therefore not correspond to the instruction bytes. However, power may be conserved by not storing and comparing the entire fetch address.

摘要翻译： 处理器包括指令高速缓存和未被主动地保持与指令高速缓存相关联的预解码高速缓存。 处理器从指令高速缓存中获取指令字节，并从预代码高速缓存预先解码信息。 基于预解码信息向多个解码单元提供指令，并且解码单元解码指令并验证预解码信息对应于指令。 更具体地，每个解码单元可以验证有效指令被解码，并且该指令成功接收由另一解码单元解码的先前指令。 此外，涉及在解码之前的指令处理流水线阶段的其他单元可以验证预解码信息的部分。 如果预解码信息不对应于获取的指令，则可以通过预编码指令字节或通过更新预解码信息来校正预解码信息，如果可以在不预编译指令字节的情况下确定更新的话）。 在一个特定实施例中，预解码高速缓存可以是存储由获取地址的一部分索引的指令指针的行预测器。 因此，线预测器可能会遇到地址混叠，因此预解码信息可能不对应于指令字节。 然而，通过不存储和比较整个读取地址可以节省功率。

公开(公告)号：US06636959B1

公开(公告)日：2003-10-21

申请号：US09416275

申请日：1999-10-14

申请人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

发明人： James B. Keller ,  Puneet Sharma ,  Keith R. Schakel ,  Francis M. Matus

IPC分类号： G06F938

CPC分类号： G06F9/382 ,  G06F9/3806 ,  G06F9/3816 ,  G06F12/0864 ,  G06F12/0875 ,  G06F2212/6082

摘要： A line predictor caches alignment information for instructions. In response to each fetch address, the line predictor provides information for the instruction beginning at the fetch address, as well as alignment information for up to one or more additional instructions subsequent to that instruction. The line predictor may include a memory having multiple entries, each entry storing up to a predefined maximum number of instruction pointers and a fetch address corresponding to the instruction identified by a first one of the instruction pointers. Since the line predictor provides alignment information from one entry per fetch, the line predictor may provide a flow control mechanism for the initial portion of the pipeline within a microprocessor. Each entry may store combinations of instructions which the hardware within the pipeline may handle without creating stalls resulting from the combinations.

摘要翻译： 行预测器缓存对齐信息的指令。 响应于每个提取地址，行预测器提供从取指址开始的指令的信息，以及在该指令之后的多达一个或多个附加指令的对齐信息。 线预测器可以包括具有多个条目的存储器，每个条目存储多达预定义的最大数量的指令指针以及与由指令指针中的第一个标识的指令相对应的读取地址。 由于线预测器提供来自每个取出的一个条目的对准信息，因此线预测器可以为微处理器内的流水线的初始部分提供流量控制机制。 每个条目可以存储管道内的硬件可以处理的指令的组合，而不会产生由组合产生的停顿。

公开(公告)号：US06687789B1

公开(公告)日：2004-02-03

申请号：US09476577

申请日：2000-01-03

申请人： James B. Keller ,  Keith R. Schakel ,  Puneet Sharma

发明人： James B. Keller ,  Keith R. Schakel ,  Puneet Sharma

IPC分类号： G06F1200

CPC分类号： G06F12/0864 ,  G06F9/30149 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F2212/6082 ,  Y02D10/13

摘要： A cache is coupled to receive an input address and a corresponding way prediction. The cache provides output bytes in response to the predicted way (instead of, performing tag comparisons to select the output bytes). Furthermore, a tag may be read from the predicted way and only partial tags are read from the non-predicted ways. The tag is compared to the tag portion of the input address, and the partial tags are compared to a corresponding partial tag portion of the input address. If the tag matches the tag portion of the input address, a hit in the predicted way is detected and the bytes provided in response to the predicted way are correct. If the tag does not match the tag portion of the input address, a miss in the predicted way is detected. If none of the partial tags match the corresponding partial tag portion of the input address, a miss in the cache is determined. On the other hand, if one or more of the partial tags match the corresponding partial tags portion of the input address, the cache searches the corresponding ways to determine whether or not the input address hits or misses in the cache.

摘要翻译： 高速缓存被耦合以接收输入地址和相应的方式预测。 缓存提供响应于预测方式的输出字节（而不是执行标签比较以选择输出字节）。 此外，可以从预测的方式读取标签，并且仅从非预测方式读取部分标签。 将标签与输入地址的标签部分进行比较，并将部分标签与输入地址的相应部分标签部分进行比较。 如果标签与输入地址的标签部分匹配，则以预测的方式检测到命中，并且响应于预测方式提供的字节是正确的。 如果标签与输入地址的标签部分不匹配，则以预测的方式检测到未命中。 如果部分标签中没有一个与输入地址的相应部分标签部分匹配，则确定高速缓存中的未命中。 另一方面，如果一个或多个部分标签与输入地址的相应部分标签部分匹配，则高速缓存搜索相应的方式以确定输入地址是否在高速缓存中命中或丢失。

公开(公告)号：US06622237B1

公开(公告)日：2003-09-16

申请号：US09476192

申请日：2000-01-03

申请人： James B. Keller ,  Thomas S. Green ,  Wei-Han Lien ,  Ramsey W. Haddad ,  Keith R. Schakel

发明人： James B. Keller ,  Thomas S. Green ,  Wei-Han Lien ,  Ramsey W. Haddad ,  Keith R. Schakel

IPC分类号： G06F900

CPC分类号： G06F9/3834 ,  G06F9/3838

摘要： A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e.g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC. A second table maintains a corresponding portion of the store PCs of recently dispatched stores, along with tags identifying the recently dispatched stores. In another implementation, the STLF predictor records a difference between the tags assigned to a load and a store which interferes with the load in a first table indexed by the load PC. The PC of the dispatching load is used to select a difference from the table, and the difference is added to the tag assigned to the load.

摘要翻译： 处理器使用存储来加载（STLF）预测器，其可以指示用于调度负载对存储的依赖性。 对于在先前执行期间干扰负载的执行的存储器，指示依赖性。 由于在存储器上指示依赖关系，所以在存储之前防止了负载的调度和/或执行。 响应于执行负载并存储和检测干扰，STLF预测器被训练用于特定负载和存储的信息。 此外，如果由STLF预测器指示负载依赖于特定存储并且实际上不发生依赖性，则STLF预测器可以是未经训练的（例如，针对特定负载的信息可以被删除）。 在一个实现中，STLF预测器在由负载PC索引的第一表中记录干扰负载的商店的PC的至少一部分。 第二个表维护最近派驻的商店的商店PC的相应部分，以及标识最近派发的商店的标签。 在另一实现中，STLF预测器记录分配给负载的标签与由负载PC索引的第一表中的负载干扰的存储器之间的差异。 调度负载的PC用于选择与表的差异，并将差值添加到分配给负载的标签。

公开(公告)号：US08744602B2

公开(公告)日：2014-06-03

申请号：US13008171

申请日：2011-01-18

申请人： Gurjeet S. Saund ,  James B. Keller ,  Michael Frank

发明人： Gurjeet S. Saund ,  James B. Keller ,  Michael Frank

IPC分类号： G05B11/01 ,  H04W4/00

CPC分类号： H04L49/10

摘要： One or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, for example. Some systems that include a hierarchical communication fabric may also include fabric control circuits that may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.

摘要翻译： 可以将一个或多个结构控制电路插入到通信结构中，以通过系统中的组件来控制通信的各个方面。 例如，结构控制电路可以包括在组件的接口到通信结构。 包括分级通信结构的一些系统还可以包括可以可选地或另外包括的结构控制电路。 织物控制电路可以是可编程的，因此可以提供调谐通信结构以满足性能和/或功能目标的能力。

公开(公告)号：US20130290681A1

公开(公告)日：2013-10-31

申请号：US13460178

申请日：2012-04-30

申请人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Sandeep Gupta

发明人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Sandeep Gupta

IPC分类号： G06F9/30

CPC分类号： G06F9/30141 ,  G06F1/3234 ,  G06F9/30112 ,  G06F9/384

摘要： A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.

摘要翻译： 一种有效降低寄存器文件访问功耗的系统和方法。 处理器可操作以执行具有两个或多个数据类型的指令，每个数据类型具有相关联的大小和对齐。 第一种数据类型的数据操作数使用等于物理寄存器文件中物理寄存器的整个宽度的操作数大小。 第二种数据类型的数据操作数使用小于物理寄存器整个宽度的操作数大小。 访问与非全宽数据类型相关的操作数的物理寄存器文件不能访问物理寄存器的全部宽度。 对于未访问的物理寄存器的部分，可以忽略给定的数值。

公开(公告)号：US08566526B2

公开(公告)日：2013-10-22

申请号：US13545526

申请日：2012-07-10

申请人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

发明人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC分类号： G06F13/00

CPC分类号： G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

摘要： In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

公开(公告)号：US20130275720A1

公开(公告)日：2013-10-17

申请号：US13447651

申请日：2012-04-16

申请人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Suparn Vats

发明人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Suparn Vats

IPC分类号： G06F9/30 ,  G06F9/312

CPC分类号： G06F9/30032 ,  G06F9/384

摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.

摘要翻译： 一种用于减少数据移动操作的延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。 如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。 此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。 特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。