公开(公告)号：US06742112B1

公开(公告)日：2004-05-25

申请号：US09473976

申请日：1999-12-29

申请人： Adi Yoaz ,  Ronny Ronen ,  Stephan J. Jourdan ,  Michael Bekerman

发明人： Adi Yoaz ,  Ronny Ronen ,  Stephan J. Jourdan ,  Michael Bekerman

IPC分类号： G06F934

CPC分类号： G06F9/30134 ,  G06F9/30167 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3842

摘要： Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.

摘要翻译： 跟踪寄存器值的装置和方法。 微处理器可以包括第一寄存器，控制电路和加法器。 第一个寄存器可以存储跟踪的寄存器值。 控制电路可以包括用于接收指令的至少一部分的指令输入和用于输出算术运算指示的第一输出。 加法器可以包括用于接收算术运算指示的控制输入，用于接收指令的立即操作数的第一输入和用于接收所跟踪的寄存器值的第二输入。

公开(公告)号：US06721849B2

公开(公告)日：2004-04-13

申请号：US10377716

申请日：2003-03-04

申请人： Stephan J. Jourdan ,  Alan Kyker

发明人： Stephan J. Jourdan ,  Alan Kyker

IPC分类号： G00F1200

CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3802 ,  G06F12/0875

摘要： Embodiments of the present invention provide a pre-decoder in a front-end system provided between an instruction cache and a decoder. The front-end system may toggle between two modes of operation. In a first mode, called the “fast mode” the front-end system retrieves pre-decoded instructions from the instruction cache and decodes them directly. In a second mode, called the “marking mode,” the front-end system retrieves data from the instruction cache and synchronizes to them prior to decoding. Synchronization results may be stored back in the instruction cache for later use.

摘要翻译： 本发明的实施例提供了在指令高速缓存和解码器之间提供的前端系统中的预解码器。 前端系统可以在两种操作模式之间切换。 在称为“快速模式”的第一模式中，前端系统从指令高速缓存中检索预解码的指令，并直接对其进行解码。 在称为“标记模式”的第二种模式中，前端系统从指令高速缓存中检索数据，并在解码之前与它们同步。 同步结果可以存储在指令高速缓存中供以后使用。

公开(公告)号：US06594754B1

公开(公告)日：2003-07-15

申请号：US09348404

申请日：1999-07-07

申请人： Stephan J. Jourdan ,  Gad S. Sheaffer ,  Ronny Ronen

发明人： Stephan J. Jourdan ,  Gad S. Sheaffer ,  Ronny Ronen

IPC分类号： G06F9315

CPC分类号： G06F9/3857 ,  G06F9/30032 ,  G06F9/30167 ,  G06F9/384

摘要： A computer architecture to process move instructions by allowing multiple mappings between logical registers and the same physical register. In one embodiment, a counter is associated with each physical register to indicate when the physical register is free. A register-to-register move instruction is processed by mapping the logical destination register of the move instruction to the same physical register to which the logical source register of the move instruction is mapped. An immediate-to-register move instruction is processed by mapping the logical destination register of the move instruction to a physical register storing the immediate.

摘要翻译： 通过允许逻辑寄存器和同一物理寄存器之间的多个映射来处理移动指令的计算机体系结构。 在一个实施例中，计数器与每个物理寄存器相关联，以指示何时物理寄存器是空闲的。 通过将移动指令的逻辑目标寄存器映射到映射了移动指令的逻辑源寄存器的同一物理寄存器来处理寄存器到寄存器移动指令。 通过将移动指令的逻辑目标寄存器映射到存储立即数的物理寄存器来处理立即注册移动指令。

公开(公告)号：US06564298B2

公开(公告)日：2003-05-13

申请号：US09742410

申请日：2000-12-22

申请人： Stephan J. Jourdan ,  Alan Kyker

发明人： Stephan J. Jourdan ,  Alan Kyker

IPC分类号： G06F1200

CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3802 ,  G06F12/0875

摘要： Embodiments of the present invention provide a pre-decoder in a front-end system provided between an instruction cache and a decoder. The front-end system may toggle between two modes of operation. In a first mode, called the “fast mode” the front-end system retrieves pre-decoded instructions from the instruction cache and decodes them directly. In a second mode, called the “marking mode,” the front-end system retrieves data from the instruction cache and synchronizes to them prior to decoding. Synchronization results may be stored back in the instruction cache for later use.

公开(公告)号：US06560690B2

公开(公告)日：2003-05-06

申请号：US09753330

申请日：2000-12-29

申请人： Herbert H. J. Hum ,  Stephan J. Jourdan ,  Deborrah Marr ,  Per H. Hammarlund

发明人： Herbert H. J. Hum ,  Stephan J. Jourdan ,  Deborrah Marr ,  Per H. Hammarlund

IPC分类号： G06F1200

CPC分类号： G06F12/1063 ,  G06F2212/656

摘要： A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address resides in the global/non-global linear-addressed cache memory, then that data block is accessed and transmitted to a requesting processor. If the data referenced by either the global/non-global linear address that was predicted correctly or the corrected global/non-global linear address does not reside in the global/non-global linear-addressed cache memory, then a cache line selected by a replacement policy has its data block replaced with a data block from a storage device at a higher hierarchical level as specified by the linear address.

公开(公告)号：US06553469B2

公开(公告)日：2003-04-22

申请号：US10153920

申请日：2002-05-24

申请人： Stephan J. Jourdan ,  Ronny Ronen ,  Michael Bekerman

发明人： Stephan J. Jourdan ,  Ronny Ronen ,  Michael Bekerman

IPC分类号： G06F1200

CPC分类号： G06F9/3806 ,  G06F12/126

摘要： Apparatus and methods to filter memory record updates. A microprocessor can include a memory record update filter. The memory record update filter can include a table memory populated by a plurality of data entries. Each data entry can include a data tag field to store a data tag, a data field to store a data value, and a filter field to store a filter value. A first comparator can be in communication with the data tag field of the table memory and a data accessing information input to perform a data tag comparison. A second comparator can be in communication with the filter field of the table memory and a data value input. A control circuit can be in communication with the table memory, the first comparator, and the second comparator.

公开(公告)号：US06516405B1

公开(公告)日：2003-02-04

申请号：US09475646

申请日：1999-12-30

申请人： Stephan J. Jourdan ,  Freddy Gabbay ,  Ronny Ronen ,  Adi Yoaz

发明人： Stephan J. Jourdan ,  Freddy Gabbay ,  Ronny Ronen ,  Adi Yoaz

IPC分类号： G06F945

CPC分类号： G06F9/30094 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863

摘要： The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.

摘要翻译： 本发明涉及一种基于控制流推测（条件分支预测）的数据压缩的装置和方法。 由于条件分支结果基于实际数据值进行解析，条件分支预测提供了对数据值的潜在有价值的洞察。 如果相等的指令遇到分支，并且如果不是相等的指令预测该指令或分支，并且该指令被预测为未被使用，则本发明假设用于确定条件分支的两个操作数相等。 数据预测是安全的，因为数据错误预测是指条件分支错误预测，导致在包括数据错误预测的条件分支指令之后的指令的流水线刷新。

公开(公告)号：US06438673B1

公开(公告)日：2002-08-20

申请号：US09475063

申请日：1999-12-30

申请人： Stephan J. Jourdan ,  Michael Bekerman ,  Ronny Ronen ,  Lihu Rappoport

发明人： Stephan J. Jourdan ,  Michael Bekerman ,  Ronny Ronen ,  Lihu Rappoport

IPC分类号： G06F1200

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F9/3832 ,  G06F12/0862 ,  G06F2212/6024

摘要： A microprocessor having a correlated address predictor, and methods of performing correlated address prediction. A first table memory can be populated by a plurality of buffer entries. Each buffer entry can include a first buffer field to store a first tag based on an instruction pointer and a second buffer field to store an address history. A second table memory can be populated by a plurality of link entries. Each link entry can include a first link field to store a link tag based on an address history and a second link field to store a predicted address. A first comparator can be in communication with the first table memory and an instruction pointer input. A second comparator can be in communication with the first table memory and the second table memory. An output in communication with the second table memory.

摘要翻译： 具有相关地址预测器的微处理器，以及执行相关地址预测的方法。 第一表存储器可以由多个缓冲器入口填充。 每个缓冲器条目可以包括基于指令指针存储第一标签的第一缓冲区域和用于存储地址历史的第二缓冲区域。 第二表存储器可以由多个链接条目填充。 每个链接条目可以包括基于地址历史存储链接标签的第一链接字段和用于存储预测地址的第二链接字段。 第一比较器可以与第一表存储器和指令指针输入通信。 第二比较器可以与第一表存储器和第二表存储器通信。 与第二表存储器通信的输出。