公开(公告)号：US11574107B2

公开(公告)日：2023-02-07

申请号：US17339162

申请日：2021-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pin-Dai Sue ,  Po-Hsiang Huang ,  Fong-Yuan Chang ,  Chi-Yu Lu ,  Sheng-Hsiung Chen ,  Chin-Chou Liu ,  Lee-Chung Lu ,  Yen-Hung Lin ,  Li-Chun Tien ,  Yi-Kan Cheng

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/394 ,  G06F111/20

Abstract: A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1st layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.

公开(公告)号：US20220352072A1

公开(公告)日：2022-11-03

申请号：US17866880

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ni-Wan Fan ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Jung-Chan Yang ,  Hsiang-Jen Tseng ,  Lipen Yuan ,  Chi-Yu Lu

IPC: H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L23/485 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/535 ,  H01L29/66

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions on or within a substrate. A first gate is arranged over the substrate between the first source/drain region and the second source/drain region. A first middle-end-of-the-line (MEOL) structure is arranged over the second source/drain region and a second MEOL structure is arranged over a third source/drain region. A conductive structure contacts the first MEOL structure and the second MEOL structure. A second gate is separated from the first gate by the second source/drain region. The conductive structure vertically and physically contacts a top surface of the second gate that is coupled to outermost sidewalls of the second gate. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the first MEOL structure along one or more conductive paths extending through the conductive structure.

公开(公告)号：US20200272781A1

公开(公告)日：2020-08-27

申请号：US16722865

申请日：2019-12-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Ming Chang ,  Ruey-Wen Chang ,  Ping-Wei Wang ,  Sheng-Hsiung Wang ,  Chi-Yu Lu

IPC: G06F30/392 ,  H01L27/11 ,  G06F30/398 ,  H01L27/088

Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.