公开(公告)号：US10438837B2

公开(公告)日：2019-10-08

申请号：US15991938

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bradley David Sucher ,  Bernard John Fischer ,  Abbas Ali

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: An electronic device includes a semiconductor substrate having a plurality of trenches formed therein. Each trench includes a sidewall having a doped region, a sidewall liner, and a filler material. The substrate has a slip density of less than 5 cm−2. The low slip density is achieved by a novel annealing protocol performed after implanting the dopant in the sidewall to repair damage and/or stress caused by the implant process.

公开(公告)号：US20190295948A1

公开(公告)日：2019-09-26

申请号：US16423723

申请日：2019-05-28

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

公开(公告)号：US10211096B1

公开(公告)日：2019-02-19

申请号：US15928492

申请日：2018-03-22

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Abbas Ali ,  Yaping Chen ,  Chao Zuo ,  Seetharaman Sridhar ,  Yunlong Liu

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L23/532

Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.

公开(公告)号：US20160149012A1

公开(公告)日：2016-05-26

申请号：US14555359

申请日：2014-11-26

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali

IPC: H01L29/45 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L29/41 ,  H01L29/06

CPC classification number: H01L29/45 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/743 ,  H01L21/763 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/41

Abstract: A semiconductor device with a very high aspect ratio contact has a deep trench in the substrate. A dielectric liner is formed on sidewalls and a bottom of the deep trench. A contact opening is formed through the dielectric liner at the bottom of the deep trench to expose the substrate, leaving the dielectric liner on the sidewalls. Electrically conductive material is formed in the deep trench to provide the very high aspect ratio contact to the substrate through the contact opening.

Abstract translation: 具有非常高的纵横比接触的半导体器件在衬底中具有深沟槽。 电介质衬垫形成在深沟槽的侧壁和底部上。 在深沟槽的底部穿过电介质衬垫形成接触开口以露出衬底，将电介质衬垫留在侧壁上。 导电材料形成在深沟槽中，以通过接触开口提供与衬底的非常高的纵横比接触。