公开(公告)号：US20240290848A1

公开(公告)日：2024-08-29

申请号：US18337527

申请日：2023-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Carlos C.J ALCANTARA ,  Chisung BAE ,  Kitae PARK ,  Mikyung KIM

IPC: H01L29/41 ,  H01L27/092

CPC classification number: H01L29/41 ,  H01L27/092

Abstract: A nanocavity-based electrode and a complementary metal-oxide-semiconductor-based device including the same are provided. In the nanocavity-based electrode, a single or a plurality of unit layers is stacked, and each unit layer includes a single or a plurality of nanocavities.

公开(公告)号：US12074247B2

公开(公告)日：2024-08-27

申请号：US17948056

申请日：2022-09-19

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Young Rag Do ,  Yeon Goog Sung

IPC: H01L33/00 ,  B82Y40/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/762 ,  H01L29/06 ,  H01L29/41

CPC classification number: H01L33/005 ,  B82Y40/00 ,  H01L21/02 ,  H01L21/2007 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/76251 ,  H01L29/06 ,  H01L29/0669 ,  H01L29/41 ,  H01L21/02543 ,  H01L21/0262

Abstract: Provided is a method of manufacturing a nanorod. The method comprising comprises the steps of: providing a growth substrate and a support substrate; epitaxially growing a nanomaterial layer onto one surface of the growth substrate; forming a sacrificial layer on one surface of the support substrate; bonding the nanomaterial layer with the sacrificial layer; separating the growth substrate from the nanomaterial layer; flattening the nanomaterial layer; forming a nanorod by etching the nanomaterial layer; and separating the nanorod by removing the sacrificial layer.

公开(公告)号：US11985857B2

公开(公告)日：2024-05-14

申请号：US18196744

申请日：2023-05-12

Applicant: Sony Group Corporation

Inventor： Hitoshi Tsuno

IPC: H01L21/00 ,  H01L21/28 ,  H01L21/66 ,  H01L27/12 ,  H01L29/41 ,  H01L29/786 ,  H01L29/788 ,  H10K59/121 ,  H10K59/131 ,  H01L21/265 ,  H01L21/285 ,  H10K59/12

CPC classification number: H10K59/1213 ,  H01L21/28 ,  H01L22/20 ,  H01L27/1251 ,  H01L29/41 ,  H01L29/786 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/788 ,  H10K59/131 ,  H01L21/26513 ,  H01L21/28556 ,  H01L27/124 ,  H01L27/1274 ,  H10K59/1201

Abstract: A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. Agate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.

公开(公告)号：US20240088228A1

公开(公告)日：2024-03-14

申请号：US18515148

申请日：2023-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Yun-Yuan WANG ,  Chih-Hsiang HSIAO ,  I-Chih NI ,  Chih-I WU

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/40 ,  H01L29/41

CPC classification number: H01L29/1045 ,  H01L29/0843 ,  H01L29/401 ,  H01L29/41

Abstract: A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.

公开(公告)号：US11887858B2

公开(公告)日：2024-01-30

申请号：US17725124

申请日：2022-04-20

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

Inventor： Shinji Nunotani ,  Shinji Onzuka

IPC: H01L21/78 ,  H01L21/304 ,  H01L21/784 ,  H01L21/268 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/417 ,  H01L29/868 ,  H01L29/872 ,  H01L21/265 ,  H01L29/45 ,  H01L29/78 ,  H01L29/739 ,  H01L21/683 ,  H01L21/283 ,  H01L29/861 ,  H01L29/41 ,  H01L29/06

CPC classification number: H01L21/3043 ,  H01L21/268 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/78 ,  H01L21/784 ,  H01L29/0657 ,  H01L29/41 ,  H01L29/417 ,  H01L29/45 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872 ,  H01L2221/68327

Abstract: A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part is provided between the first and second electrodes. A method of manufacturing the device includes forming the first electrode covering a back surface of a wafer after the second electrode is formed on a front surface of the wafer; forming a first groove by selectively removing the first electrode; and dividing the wafer by forming a second groove at the front surface side. The wafer includes a region to be the semiconductor part; and the first and second grooves are provided along a periphery of the region. The first groove is in communication with the first groove. The second groove has a width in a direction along the front surface of the wafer, the width of the first groove being narrower than a width of the first groove in the same direction.

公开(公告)号：US11855150B2

公开(公告)日：2023-12-26

申请号：US17827543

申请日：2022-05-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Yun-Yuan Wang ,  Chih-Hsiang Hsiao ,  I-Chih Ni ,  Chih-I Wu

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/41 ,  H01L29/40

CPC classification number: H01L29/1045 ,  H01L29/0843 ,  H01L29/401 ,  H01L29/41

Abstract: A device includes a substrate, a channel layer, a barrier layer, a gate electrode, and source/drain contacts. The channel layer is made of transition metal dichalcogenide. The barrier layer is over the channel layer. The gate electrode is over the barrier layer. The source/drain contacts are on opposite sides of the gate electrode and over the barrier layer.

公开(公告)号：US20190051724A1

公开(公告)日：2019-02-14

申请号：US16077316

申请日：2017-02-24

Applicant: PSI CO., LTD.

Inventor： Young Rag DO ,  Yeon Goog SUNG

IPC: H01L29/06 ,  H01L21/762 ,  B82Y40/00

CPC classification number: H01L29/0669 ,  B82Y40/00 ,  H01L21/02 ,  H01L21/2007 ,  H01L21/205 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3063 ,  H01L21/76251 ,  H01L29/06 ,  H01L29/41

Abstract: Provided is a method of manufacturing a nanorod. The method comprising comprises the steps of: providing a growth substrate and a support substrate; epitaxially growing a nanomaterial layer onto one surface of the growth substrate; forming a sacrificial layer on one surface of the support substrate; bonding the nanomaterial layer with the sacrificial layer;separating the growth substrate from the nanomaterial layer; flattening the nanomaterial layer; forming a nanorod by etching the nanomaterial layer; and separating the nanorod by removing the sacrificial layer.

公开(公告)号：US20180358469A1

公开(公告)日：2018-12-13

申请号：US15778270

申请日：2016-11-14

Applicant: Sharp Kabushiki Kaisha

Inventor： Seiichi UCHIDA ,  Kuniaki OKADA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/24 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L29/7869 ,  G02F1/1343 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/40 ,  G09F9/30 ,  H01L21/28 ,  H01L27/1225 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/127 ,  H01L29/24 ,  H01L29/41 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device (1001) includes: a thin film transistor (101) including an oxide semiconductor layer (16) including a channel region, and a source contact region and a drain contact region arranged on opposite sides of the channel region; an insulating layer arranged so as to cover the oxide semiconductor layer (16), the insulating layer having a contact hole (CH) through which the drain contact region is exposed; and a transparent electrode (24) to be in contact with the drain contact region in the contact hole (CH), wherein: as seen from a direction normal to the substrate, at least a part R of the drain contact region overlaps a gate electrode (12); and on an arbitrary cross section that extends in a channel width direction across the at least part (R) of the drain contact region, a width of the oxide semiconductor layer (16) is greater than a width of the gate electrode (12), and the gate electrode (12) is covered by the oxide semiconductor layer (16) with the gate insulating layer therebetween.

公开(公告)号：US10056311B2

公开(公告)日：2018-08-21

申请号：US15655070

申请日：2017-07-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshihito Otsubo ,  Muneyoshi Yamamoto ,  Norio Sakai

IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L23/14 ,  H05K1/18 ,  H01L23/495 ,  H01L23/28 ,  H01L29/41 ,  H01L23/498

CPC classification number: H01L23/14 ,  H01L21/561 ,  H01L23/13 ,  H01L23/28 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49572 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/52 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/97 ,  H01L29/41 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15159 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K1/0218 ,  H05K1/0298 ,  H05K1/188 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/0715 ,  H05K2203/1316 ,  H01L2224/81 ,  H01L2924/00012

Abstract: An electronic circuit module includes a circuit board, electronic components, an embedding layer, and a conductive film. The circuit board has a first principal surface, a second principal surface and a side surface, and includes a pattern conductor and a via conductor. The conductive film is connected to a conduction path to a ground electrode. The side surface includes a first region, a second region having a longer circumferential length than the first region, and a connection region connecting the first region and the second regions. The conductive film is formed on a region including at least part of each of an outer surface of the embedding layer, the first region, and the connection region. The conductive film formed on at least part of the connection region is connected to an exposed portion in the connection region of the via conductor included in the conduction path to the ground electrode.

公开(公告)号：US20180166542A1

公开(公告)日：2018-06-14

申请号：US15800538

申请日：2017-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hoon KIM

IPC: H01L29/40 ,  H01L27/02 ,  H01L29/41 ,  H01L49/02 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L29/401 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76801 ,  H01L23/64 ,  H01L27/0207 ,  H01L27/108 ,  H01L28/60 ,  H01L28/91 ,  H01L29/41

Abstract: A semiconductor device including a plurality of lower electrodes on a substrate, the plurality of lower electrodes in a first direction and a second direction perpendicular to the first direction to form rows and columns, a support structure having a flat panel form, the support structure connecting and supporting the plurality of lower electrodes, the support structure including a plurality of open areas defined therein, the support structure including two different shapes in an alternating manner may be provided. The plurality of open areas may have a same shape and partially expose sides of all the plurality of lower electrodes.