公开(公告)号：US10483157B2

公开(公告)日：2019-11-19

申请号：US16049715

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hsuan Hsiao ,  Yee-Chia Yeo ,  Tung Ying Lee ,  Chih Chieh Yeh

IPC: H01L29/41 ,  H01L21/768 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/108 ,  H01L29/78

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US10290546B2

公开(公告)日：2019-05-14

申请号：US15666715

申请日：2017-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28 ,  H01L29/49

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US10147819B2

公开(公告)日：2018-12-04

申请号：US15464484

申请日：2017-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng Chen ,  Chih Chieh Yeh ,  Cheng-Hsien Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10

Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on each of the first channel layers, a gate electrode layer disposed on the gate dielectric. Each of the first channel layers includes a semiconductor wire made of a first semiconductor material. The semiconductor wire passes through the first source/drain region and enters into an anchor region. At the anchor region, the semiconductor wire has no gate electrode layer and no gate dielectric, and is sandwiched by a second semiconductor material.

公开(公告)号：US20180151438A1

公开(公告)日：2018-05-31

申请号：US15666715

申请日：2017-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Szu-Wei Huang ,  Huan-Sheng Wei ,  Jon-Hsu Ho ,  Chih Chieh Yeh ,  Wen-Hsing Hsieh ,  Chung-Cheng Wu ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823412 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78651 ,  H01L29/78696

Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.

公开(公告)号：US09741829B2

公开(公告)日：2017-08-22

申请号：US14714227

申请日：2015-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Peng ,  Chih Chieh Yeh ,  Chih-Sheng Chang ,  Hung-Li Chiang ,  Hung-Ming Chen ,  Yee-Chia Yeo

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/41725 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.