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    Methods and systems for improving a maximum operating frequency of an integrated circuit during a route phase
    52.
    发明授权
    Methods and systems for improving a maximum operating frequency of an integrated circuit during a route phase 有权
    用于在路线阶段期间提高集成电路的最大工作频率的方法和系统

    公开(公告)号：US08191028B1

    公开(公告)日：2012-05-29

    申请号：US12419986

    申请日：2009-04-07

    申请人： Mark Bourgeault ,  Vaughn Betz

    发明人： Mark Bourgeault ,  Vaughn Betz

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5077

    摘要： Mechanisms are provided to improve maximum operating frequency in an integrated circuit. Optimization may be performed during a route phase of a compilation process performed to generate a configuration of the integrated circuit. In some instances, useful clock skew is automatically determined and clock connectivity is rewired on a per-integrated circuit block (per-LAB) basis during the route phase.

    摘要翻译： 提供了用于提高集成电路中的最大工作频率的机制。 可以在执行用于生成集成电路的配置的编译处理的路由阶段期间执行优化。 在某些情况下，在路由阶段期间，自动确定有用的时钟偏移，并在每个集成电路块（每个LAB）上重新布线时钟连接。

    Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability
    54.
    发明授权
    Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability 有权
    优化长途径和短路时间，并对制造和运行状况变化进行考虑

    公开(公告)号：US07725853B1

    公开(公告)日：2010-05-25

    申请号：US11857316

    申请日：2007-09-18

    申请人： Ryan Fung ,  Vaughn Betz

    发明人： Ryan Fung ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： Logic designs are optimized to satisfy long-path and short-path timing constraints for multiple process/operating condition corners. A path-based compilation phase determines an implementation for logic design paths, in part, by monitoring a set of paths that are important from a timing perspective and evaluating the timing performance of the set of monitored paths at one or more timing corners. A timing-analysis-based compilation phase determines transformations for converting sets of timing values from one timing corner to another timing corner. The compilation phase transforms timing delay values from one timing corner to another to facilitate analysis of timing performance at different corners. Timing slack values produced by analysis are transformed to map them from one timing corner to another. The transformed timing slack values from multiple corners are amalgamated. The amalgamated timing slack values are used by a compilation phase (that potentially only understands a single corner) to optimize a logic design for multiple corners.

    摘要翻译： 优化逻辑设计，以满足多个过程/操作条件角的长途径和短路时序约束。 基于路径的编译阶段确定逻辑设计路径的实现，部分地通过监视从时序角度重要的一组路径并且评估一个或多个定时角上的一组被监控路径的定时性能。 基于时序分析的编译阶段确定将一组定时值从一个定时角转换到另一个时间角的转换。 编译阶段将时序延迟值从一个定时角转换到另一个定时角，以便于分析不同角落的时序性能。 通过分析产生的时间松弛值被转换，以将它们从一个时间点转到另一个时间点。 来自多个角落的转换后的时间松弛值是合并的。 合并的定时松弛值由编译阶段（可能只能理解单个角）使用，以优化多个角的逻辑设计。

    Apparatus and Methods for Parallelizing Integrated Circuit Computer-Aided Design Software
    55.
    发明申请
    Apparatus and Methods for Parallelizing Integrated Circuit Computer-Aided Design Software 审中-公开
    并联集成电路计算机辅助设计软件的装置与方法

    公开(公告)号：US20100070979A1

    公开(公告)日：2010-03-18

    申请号：US12545224

    申请日：2009-08-21

    申请人： Adrian Ludwin ,  Vaughn Betz ,  Ketan Padalia

    发明人： Adrian Ludwin ,  Vaughn Betz ,  Ketan Padalia

    IPC分类号： G06F9/46

    CPC分类号： G06F9/4881 ,  G06F2209/483 ,  G06F2209/484

    摘要： A system for parallelizing software in computer-aided design (CAD) software for logic design includes a computer. The computer is configured to identify dependencies among a set of tasks. The computer is also configured to perform the set of tasks in parallel such that a solution of a problem is identical to a solution produced by performing the set of tasks serially.

    摘要翻译： 用于并行化用于逻辑设计的计算机辅助设计（CAD）软件中的软件的系统包括计算机。 计算机被配置为识别一组任务之间的依赖关系。 计算机还被配置为并行地执行一组任务，使得问题的解决方案与通过一致地执行该任务所产生的解决方案相同。

    Systems and methods for reducing static and total power consumption in a programmable logic device
    56.
    发明授权
    Systems and methods for reducing static and total power consumption in a programmable logic device 失效
    用于减少可编程逻辑器件中的静态和总功耗的系统和方法

    公开(公告)号：US07467314B2

    公开(公告)日：2008-12-16

    申请号：US11642287

    申请日：2006-12-19

    申请人： David Mendel ,  Vaughn Betz

    发明人： David Mendel ,  Vaughn Betz

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/32

    摘要： A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.

    摘要翻译： 提供了一种用于降低可编程逻辑器件（PLD）中功耗的方法和系统。 在可编程逻辑器件的技术映射，路由和后续周期期间，优选地可以连续地考虑功率消耗作为电路设计中的一个因素来降低功耗。

    Methods for designing integrated circuits
    57.
    发明授权
    Methods for designing integrated circuits 有权
    集成电路设计方法

    公开(公告)号：US07441208B1

    公开(公告)日：2008-10-21

    申请号：US11225919

    申请日：2005-09-13

    申请人： Ketan Padalia ,  Vaughn Betz ,  Vadim Gouterman

    发明人： Ketan Padalia ,  Vaughn Betz ,  Vadim Gouterman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： The process of designing an integrated circuit (“IC”) to implement a generalized circuit design includes a signoff between a front-end part of the process and a back-end part of the process. This signoff preferably takes place after at least some global routing has been done for the IC implementation, but before all final detailed routing is done for that implementation.

    摘要翻译： 设计集成电路（“IC”）以实现广义电路设计的过程包括过程的前端部分与过程的后端部分之间的签名。 这种签名优选在对IC实现进行至少一些全局路由之后，但在为该实现完成所有最终详细路由之前进行。

    Apparatus and methods for parallelizing integrated circuit computer-aided design software
    59.
    发明申请
    Apparatus and methods for parallelizing integrated circuit computer-aided design software 审中-公开
    用于并行集成电路计算机辅助设计软件的装置和方法

    公开(公告)号：US20070192766A1

    公开(公告)日：2007-08-16

    申请号：US11392215

    申请日：2006-03-29

    申请人： Ketan Padalia ,  Adrian Ludwin ,  Vaughn Betz ,  Ryan Fung

    发明人： Ketan Padalia ,  Adrian Ludwin ,  Vaughn Betz ,  Ryan Fung

    IPC分类号： G06F9/46

    CPC分类号： G06F8/45 ,  G06F17/5054

    摘要： A system for providing parallelization in computer aided design (CAD) software includes a computer. The computer is configured to identify a set of tasks having local independence, and assign each task in the set of tasks to be performed in parallel. The computer is further configured to perform each task in the set of tasks.

    摘要翻译： 用于在计算机辅助设计（CAD）软件中提供并行化的系统包括计算机。 计算机被配置为识别具有本地独立性的一组任务，并且将要并行执行的任务集中的每个任务分配。 计算机还被配置为在该组任务中执行每个任务。

    Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability
    60.
    发明授权
    Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability 有权

    公开(公告)号：US07254789B1

    公开(公告)日：2007-08-07

    申请号：US11002977

    申请日：2004-12-01

    申请人： Ryan Fung ,  Vaughn Betz

    发明人： Ryan Fung ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/5045

    摘要： Logic designs are optimized to satisfy long-path and short-path timing constraints for multiple process/operating condition corners. A path-based compilation phase determines an implementation for logic design paths, in part, by monitoring a set of paths that are important from a timing perspective and evaluating the timing performance of the set of monitored paths at one or more timing corners. A timing-analysis-based compilation phase determines transformations for converting sets of timing values from one timing corner to another timing corner. The compilation phase transforms timing delay values from one timing corner to another to facilitate analysis of timing performance at different corners. Timing slack values produced by analysis are transformed to map them from one timing corner to another. The transformed timing slack values from multiple corners are amalgamated. The amalgamated timing slack values are used by a compilation phase (that potentially only understands a single corner) to optimize a logic design for multiple corners.