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    Methods and systems for improving a maximum operating frequency of an integrated circuit during a route phase
    4.
    发明授权
    Methods and systems for improving a maximum operating frequency of an integrated circuit during a route phase 有权
    用于在路线阶段期间提高集成电路的最大工作频率的方法和系统

    公开(公告)号：US08191028B1

    公开(公告)日：2012-05-29

    申请号：US12419986

    申请日：2009-04-07

    申请人： Mark Bourgeault ,  Vaughn Betz

    发明人： Mark Bourgeault ,  Vaughn Betz

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5077

    摘要： Mechanisms are provided to improve maximum operating frequency in an integrated circuit. Optimization may be performed during a route phase of a compilation process performed to generate a configuration of the integrated circuit. In some instances, useful clock skew is automatically determined and clock connectivity is rewired on a per-integrated circuit block (per-LAB) basis during the route phase.

    摘要翻译： 提供了用于提高集成电路中的最大工作频率的机制。 可以在执行用于生成集成电路的配置的编译处理的路由阶段期间执行优化。 在某些情况下，在路由阶段期间，自动确定有用的时钟偏移，并在每个集成电路块（每个LAB）上重新布线时钟连接。

    Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions
    5.
    发明授权
    Method for programming programmable logic device with blocks that perform multiplication and other arithmetic functions 失效
    使用执行乘法和其他算术功能的程序段编程可编程逻辑器件的方法

    公开(公告)号：US06971083B1

    公开(公告)日：2005-11-29

    申请号：US10294234

    申请日：2002-11-13

    申请人： Jennifer Farrugia ,  Elias Ahmed ,  Mark Bourgeault

    发明人： Jennifer Farrugia ,  Elias Ahmed ,  Mark Bourgeault

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： A programming method efficiently programs programmable logic devices of the type having specialized multiplier blocks that include multipliers and other arithmetic function elements. Such blocks can be used to perform certain multiplication and multiplication-related functions more efficiently than general-purpose programmable logic. In order to efficiently program devices having such specialized multiplier blocks, so that they are used to their full potential and so that the maximum number of multiplier-related functions can be accommodated on a single programmable logic device, the programming method pre-processes the netlist of function blocks in a user's programmable logic design, grouping multiplication and multiplication-related functions efficiently. The method takes into account limitations imposed by the structure of the specialized multiplier blocks, in addition to location constraints imposed by the user and location constraints dictated by the need for certain functions be carried out near where certain other functions are carried out.

    摘要翻译： 编程方法有效地编程具有包括乘法器和其他算术功能元件的专用乘法器块的类型的可编程逻辑器件。 这样的块可以用于比通用可编程逻辑更有效地执行某些乘法和乘法相关函数。 为了有效地对具有这种专用乘法器块的器件进行编程，使得它们被用于其全部潜能，并且使得乘法器相关功能的最大数量可以被容纳在单个可编程逻辑器件上，编程方法预处理网表 的用户可编程逻辑设计中的功能块，有效地对乘法和乘法相关函数进行分组。 该方法除了由用户施加的位置约束以及由执行特定功能附近执行某些功能所需的位置约束之外，还考虑了由专用乘法器块的结构施加的限制。

    Automatic asynchronous signal pipelining
    7.
    发明授权
    Automatic asynchronous signal pipelining 有权

    公开(公告)号：US08539414B1

    公开(公告)日：2013-09-17

    申请号：US12651982

    申请日：2010-01-04

    申请人： Mark Bourgeault ,  Ryan Fung ,  David Lewis

    发明人： Mark Bourgeault ,  Ryan Fung ,  David Lewis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/00323 ,  H03K19/17736

    摘要： An electronic design automation (EDA) tool alters a user's netlist to provide timing success for distribution of asynchronous signals. Distribution networks are used with the addition of pipeline registers before and/or after the distribution buffer. Or, a tree of pipeline registers is inserted between the asynchronous source and the destination registers. Or, any number of distribution networks are stitched together and pipeline stages may be inserted before and/or after each distribution buffer. Or, beneficial skew is utilized by introducing a delay component that skews a clock signal. The skewed clock signal drives a pipeline register that is inserted before a distribution buffer in order to improve timing margin. Any of various compilation techniques may be used within the EDA tool to solve the problem of distributing high-speed, high-fanout asynchronous signals. The technique has utility for high-performance FPGAs and structured ASIC families, as well as for low-cost FPGAs and other types of logic devices.

    Preventing information leakage between components on a programmable chip in the presence of faults
    8.
    发明授权
    Preventing information leakage between components on a programmable chip in the presence of faults 有权
    在存在故障的情况下防止可编程芯片上的组件之间的信息泄漏

    公开(公告)号：US08356358B2

    公开(公告)日：2013-01-15

    申请号：US12631588

    申请日：2009-12-04

    申请人： David Samuel Goldman ,  Mark Bourgeault

    发明人： David Samuel Goldman ,  Mark Bourgeault

    IPC分类号： G06F17/50 ,  G06F21/00

    CPC分类号： G06F21/76 ,  G06F17/5054 ,  G06F17/5077 ,  G06F2217/70 ,  G09C1/00

    摘要： Mechanisms are provided to prevent information leakage between components implemented on a programmable chip such as a Field Programmable Gate Array (FPGA). An automated routing algorithm is effective at enforcing security restrictions with minimal input form the user while providing efficient utilization of the device. Compatible sets of signals are identified and locked, and reservations of routing resources are generated. Remaining signals are rerouted until all signal constraints are met. Specified security constraints with one or more security levels and one or more secure regions may be applied through iterations of the automated routing mechanism.

    摘要翻译： 提供了用于防止在诸如现场可编程门阵列（FPGA）的可编程芯片上实现的组件之间的信息泄漏的机制。 自动路由算法在提供对设备的有效利用的同时以用户的最小输入来实施安全限制是有效的。 识别和锁定兼容的信号集，并生成路由资源的预留。 剩余信号被重新路由，直到满足所有信号约束。 可以通过迭代自动路由机制来应用具有一个或多个安全级别和一个或多个安全区域的指定的安全约束。

    PREVENTING INFORMATION LEAKAGE BETWEEN COMPONENTS ON A PROGRAMMABLE CHIP IN THE PRESENCE OF FAULTS
    9.
    发明申请
    PREVENTING INFORMATION LEAKAGE BETWEEN COMPONENTS ON A PROGRAMMABLE CHIP IN THE PRESENCE OF FAULTS 有权
    防止故障存在时可编程芯片组件之间的信息泄漏

    公开(公告)号：US20110138223A1

    公开(公告)日：2011-06-09

    申请号：US12631588

    申请日：2009-12-04

    申请人： David Samuel Goldman ,  Mark Bourgeault

    发明人： David Samuel Goldman ,  Mark Bourgeault

    IPC分类号： G06F11/07

    CPC分类号： G06F21/76 ,  G06F17/5054 ,  G06F17/5077 ,  G06F2217/70 ,  G09C1/00

    摘要： Mechanisms are provided to prevent information leakage between components implemented on a programmable chip such as a Field Programmable Gate Array (FPGA). An automated routing algorithm is effective at enforcing security restrictions with minimal input form the user while providing efficient utilization of the device. Compatible sets of signals are identified and locked, and reservations of routing resources are generated. Remaining signals are rerouted until all signal constraints are met. Specified security constraints with one or more security levels and one or more secure regions may be applied through iterations of the automated routing mechanism.

    摘要翻译： 提供了用于防止在诸如现场可编程门阵列（FPGA）的可编程芯片上实现的组件之间的信息泄漏的机制。 自动路由算法在提供对设备的有效利用的同时以用户的最小输入来实施安全限制是有效的。 识别和锁定兼容的信号集，并生成路由资源的预留。 剩余信号被重新路由，直到满足所有信号约束。 可以通过迭代自动路由机制来应用具有一个或多个安全级别和一个或多个安全区域的指定的安全约束。

    Automatic asynchronous signal pipelining
    10.
    发明授权
    Automatic asynchronous signal pipelining 有权
    自动异步信号流水线

    公开(公告)号：US07676768B1

    公开(公告)日：2010-03-09

    申请号：US11437950

    申请日：2006-05-19

    申请人： Mark Bourgeault ,  Ryan Fung ,  David Lewis

    发明人： Mark Bourgeault ,  Ryan Fung ,  David Lewis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/84 ,  H03K19/00323 ,  H03K19/17736

    摘要： An electronic design automation (EDA) tool alters a user's netlist to provide timing success for distribution of asynchronous signals. Distribution networks are used with the addition of pipeline registers before and/or after the distribution buffer. Or, a tree of pipeline registers is inserted between the asynchronous source and the destination registers. Or, any number of distribution networks are stitched together and pipeline stages may be inserted before and/or after each distribution buffer. Or, beneficial skew is utilized by introducing a delay component that skews a clock signal. The skewed clock signal drives a pipeline register that is inserted before a distribution buffer in order to improve timing margin. Any of various compilation techniques may be used within the EDA tool to solve the problem of distributing high-speed, high-fanout asynchronous signals. The technique has utility for high-performance FPGAs and structured ASIC families, as well as for low-cost FPGAs and other types of logic devices.

    摘要翻译： 电子设计自动化（EDA）工具改变用户的网表以提供异步信号分配的时序成功。 分配网络在分配缓冲区之前和/或之后添加流水线寄存器时使用。 或者，在异步源和目标寄存器之间插入一条流水线寄存器树。 或者，任何数量的分发网络被缝合在一起，并且可以在每个分发缓冲器之前和/或之后插入流水线阶段。 或者，通过引入偏移时钟信号的延迟分量来利用有益的偏移。 偏斜时钟信号驱动在分配缓冲器之前插入的流水线寄存器，以便提高定时裕度。 可以在EDA工具中使用各种编译技术中的任何一种来解决分配高速，高扇出异步信号的问题。 该技术可用于高性能FPGA和结构化ASIC系列，以及低成本FPGA和其他类型的逻辑器件。