公开(公告)号：US20220108953A1

公开(公告)日：2022-04-07

申请号：US17314055

申请日：2021-05-07

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tzyy-Jang Tseng ,  Ra-Min Tain ,  Kai-Ming Yang

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48

Abstract: A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.

公开(公告)号：US20220069489A1

公开(公告)日：2022-03-03

申请号：US17319109

申请日：2021-05-13

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Chia-Yu Peng ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: H01R12/52 ,  H01L21/48 ,  H01L23/498 ,  H01R4/04 ,  H01R43/00

Abstract: A circuit board structure, including a redistribution circuit structure layer, a build-up circuit structure layer, and a connection structure layer, is provided. The redistribution circuit structure layer includes multiple first connecting pads. The build-up circuit structure layer is disposed on one side of the redistribution circuit structure layer and includes multiple second connecting pads. A line width and a line spacing of the redistribution circuit structure layer are smaller than a line width and a line spacing of the build-up circuit structure layer. The connection structure layer is disposed between the redistribution circuit structure layer and the build-up circuit structure layer, and includes a substrate and multiple conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads respectively through the conductive paste pillars. The first connecting pads and the second connecting pads are respectively embedded in two opposite surfaces of the substrate.

公开(公告)号：US20210251107A1

公开(公告)日：2021-08-12

申请号：US17017702

申请日：2020-09-11

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  Pu-Ju Lin ,  Cheng-Chung Lo ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng ,  John Hon-Shing Lau

IPC: H05K7/20 ,  F28D15/02 ,  F28D15/04 ,  B21D53/08

Abstract: A vapor chamber structure includes a thermally conductive housing, a capillary structure layer, a grid structure layer, and a working fluid. The thermally conductive housing has a sealed chamber, where a pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer is disposed in the sealed chamber. The grid structure layer is disposed in the sealed chamber and arranged along a first direction. A size of the grid structure layer is less than or equal to a size of the capillary structure layer. The working fluid fills the sealed chamber.

公开(公告)号：US20210136931A1

公开(公告)日：2021-05-06

申请号：US17147474

申请日：2021-01-13

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tse-Wei Wang

IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11 ,  H05K1/03

Abstract: A manufacturing method of a carrier structure includes: A build-up circuit layer is formed on a carrier. The build-up circuit layer includes at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on the carrier and includes at least one first pad, which is disposed relative to at least one through hole of the carrier. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive via penetrates the first dielectric layer and is electrically connected to the first circuit layer and the second circuit layer.

公开(公告)号：US10925172B1

公开(公告)日：2021-02-16

申请号：US16702478

申请日：2019-12-03

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tse-Wei Wang

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K1/03

Abstract: A carrier structure includes a carrier having at least one through hole penetrating the carrier and a build-up circuit layer located on the carrier and including at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on a first surface of the carrier and includes at least one first pad disposed relative to the through hole. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive vias penetrate the first dielectric layer and are electrically connected to the first and second circuit layers.

公开(公告)号：US10685922B2

公开(公告)日：2020-06-16

申请号：US16240806

申请日：2019-01-07

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Cheng-Ta Ko ,  Yu-Hua Chen ,  Tzyy-Jang Tseng ,  Ra-Min Tain

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01L23/31

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

公开(公告)号：US20190306987A1

公开(公告)日：2019-10-03

申请号：US16361180

申请日：2019-03-21

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Kai-Ming Yang ,  Chih-Lun Wang

IPC: H05K1/18 ,  H05K1/09 ,  H05K1/11 ,  H05K3/46 ,  H05K3/42 ,  H05K3/00 ,  H05K1/02

Abstract: A circuit board including an interconnect substrate and a multilayer structure is provided. The interconnect substrate includes a core layer and a conductive structure disposed on the core layer. The multilayer structure is disposed on the conductive structure. The multilayer structure includes a plurality of dielectric layers and a plurality of circuit structures. The circuit structures are disposed in the dielectric layers. A topmost layer in the circuit structures is exposed to the dielectric layers to be in contact with the conductive structure. A pattern of the topmost layer in the circuit structures and a pattern of a top surface of the conductive structure are engaged with each other.

公开(公告)号：US12243838B2

公开(公告)日：2025-03-04

申请号：US17567883

申请日：2022-01-04

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  John Hon-Shing Lau

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A circuit substrate structure includes a circuit substrate, at least two chips, and a bridge element. The circuit substrate has a first surface and a second surface opposite to each other. The chips are arranged in parallel on the first surface of the circuit substrate and electrically connected to the circuit substrate. The chips have active surfaces, back surfaces opposite to the active surfaces, and side surfaces connecting the active surfaces and the back surfaces. The chips include side circuits. The side circuits are arranged on the side surfaces and have first ends and second ends, the first ends extend to the active surfaces along the side surfaces, and the second ends extend to the back surfaces along the side surfaces. The bridge element is arranged on the back surfaces of the chips and electrically connected to the active surfaces of the chips through the side circuits.

公开(公告)号：US12160953B2

公开(公告)日：2024-12-03

申请号：US17992933

申请日：2022-11-23

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/46

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

公开(公告)号：US20240248264A1

公开(公告)日：2024-07-25

申请号：US18623035

申请日：2024-04-01

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: G02B6/42 ,  G02B6/12 ,  H01L23/498 ,  H01L25/065

CPC classification number: G02B6/4206 ,  G02B6/12004 ,  G02B6/4293 ,  H01L23/49816 ,  H01L25/0652

Abstract: Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.