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公开(公告)号:US11516910B1
公开(公告)日:2022-11-29
申请号:US17371114
申请日:2021-07-09
发明人: Chia-Yu Peng , John Hon-Shing Lau , Kai-Ming Yang , Pu-Ju Lin , Cheng-Ta Ko , Tzyy-Jang Tseng
摘要: A circuit board structure includes a redistribution structure layer, a build-up circuit structure layer, and a connection structure layer. The redistribution structure layer has a first and second surface, and includes an inner and outer dielectric layer, first connecting pads, and chip pads. A bottom surface of each first connecting pad is aligned with the first surface, and the chip pads are protruded from and located on the second surface. The build-up circuit structure layer includes second connecting pads. The connection structure layer is disposed between the redistribution structure layer and the build-up circuit structure layer and includes a substrate and conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads via the conductive paste pillars, respectively. A top surface of each conductive paste pillar is aligned with the first surface of the redistribution structure layer.
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公开(公告)号:US20220344248A1
公开(公告)日:2022-10-27
申请号:US17235944
申请日:2021-04-21
发明人: John Hon-Shing Lau , Cheng-Ta Ko , Pu-Ju Lin , Kai-Ming Yang , Chi-Hai Kuo , Chia-Yu Peng , Tzyy-Jang Tseng
IPC分类号: H01L23/498 , H01L25/065 , H01L23/538 , H01L23/00 , H01L23/31 , H01L21/48 , H01L21/56
摘要: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.
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公开(公告)号:US20220256717A1
公开(公告)日:2022-08-11
申请号:US17234805
申请日:2021-04-20
发明人: John Hon-Shing Lau , Cheng-Ta Ko , Pu-Ju Lin , Chi-Hai Kuo , Kai-Ming Yang , Chia-Yu Peng , Shao-Chien Lee , Tzyy-Jang Tseng
摘要: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.
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公开(公告)号:US20220336333A1
公开(公告)日:2022-10-20
申请号:US17233551
申请日:2021-04-19
发明人: John Hon-Shing Lau , Cheng-Ta Ko , Pu-Ju Lin , Kai-Ming Yang , Chia-Yu Peng , Chi-Hai Kuo , Tzyy-Jang Tseng
IPC分类号: H01L23/498 , H01L21/48 , H01L23/00
摘要: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.
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公开(公告)号:US20220208630A1
公开(公告)日:2022-06-30
申请号:US17155094
申请日:2021-01-22
发明人: Kai-Ming Yang , Chia-Yu Peng , Pei-Chi Chen , Pu-Ju Lin , Cheng-Ta Ko
IPC分类号: H01L23/31 , H01L23/498 , H01L21/56 , H01L21/78
摘要: A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.
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公开(公告)号:US20220328387A1
公开(公告)日:2022-10-13
申请号:US17232128
申请日:2021-04-15
发明人: John Hon-Shing Lau , Cheng-Ta Ko , Pu-Ju Lin , Kai-Ming Yang , Chi-Hai Kuo , Chia-Yu Peng , Tzyy-Jang Tseng
IPC分类号: H01L23/498 , H01L21/48 , H01L21/683
摘要: A package carrier includes a first redistribution layer having a first upper surface and a first lower surface and including a plurality of first redistribution circuits, a plurality of conductive through holes, a plurality of photoimageable dielectric layers, and a plurality of chip pads and a second redistribution layer disposed on the first upper surface of the first redistribution layer. The second redistribution layer has a second upper surface and a second lower surface aligned with and directly connected to the first upper surface of the first redistribution layer and includes a plurality of second redistribution circuits, a plurality of conductive structures, a plurality of Ajinomoto build-up Film (ABF) layers, and a plurality of solder ball pads. A line width and a line pitch of each of the first redistribution circuits are smaller than a line width and a line pitch of each of the second redistribution circuits.
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公开(公告)号:US20220069489A1
公开(公告)日:2022-03-03
申请号:US17319109
申请日:2021-05-13
发明人: John Hon-Shing Lau , Chia-Yu Peng , Kai-Ming Yang , Pu-Ju Lin , Cheng-Ta Ko , Tzyy-Jang Tseng
IPC分类号: H01R12/52 , H01L21/48 , H01L23/498 , H01R4/04 , H01R43/00
摘要: A circuit board structure, including a redistribution circuit structure layer, a build-up circuit structure layer, and a connection structure layer, is provided. The redistribution circuit structure layer includes multiple first connecting pads. The build-up circuit structure layer is disposed on one side of the redistribution circuit structure layer and includes multiple second connecting pads. A line width and a line spacing of the redistribution circuit structure layer are smaller than a line width and a line spacing of the build-up circuit structure layer. The connection structure layer is disposed between the redistribution circuit structure layer and the build-up circuit structure layer, and includes a substrate and multiple conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads respectively through the conductive paste pillars. The first connecting pads and the second connecting pads are respectively embedded in two opposite surfaces of the substrate.
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