公开(公告)号：US20210074832A1

公开(公告)日：2021-03-11

申请号：US16951361

申请日：2020-11-18

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092

Abstract: Provided is a manufacturing method of s semiconductor structure. The method includes: providing a substrate, wherein the substrate has a plurality of fin portions and at least one recessed portion, the at least one recessed portion is located between two adjacent fin portions of the plurality of fin portions and a bottom surface of the at least one recessed portion is lower than a surface of the substrate between the two of the plurality of fin portions; forming a doping layer on a sidewall of the plurality of fin portions, the surface of the substrate, and a sidewall and a bottom portion of the at least one recessed portion; and forming a dielectric layer on the doping layer. A top surface of the doping layer and a top surface of the dielectric layer are lower than a top surface of each of the plurality of fin portions.

公开(公告)号：US10566290B2

公开(公告)日：2020-02-18

申请号：US15715184

申请日：2017-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun ,  Yu-Cheng Tung ,  Sheng-Yuan Hsueh ,  Fan-Wei Lin

IPC: H01L23/544 ,  H01L21/66 ,  G01B21/24 ,  G03F7/20 ,  G01B21/20 ,  G03F9/00

Abstract: The present invention provides an alignment mark, the alignment mark includes at least one dummy mark pattern in a first layer comprises a plurality of dummy mark units arranged along a first direction, and at least one first mark pattern located in a second layer disposed above the first layer, the first mark pattern comprises a plurality of first mark units, each of the first mark units being arranged in a first direction. When viewed in a top view, the first mark pattern completely covers the dummy mark pattern, and the size of each dummy mark unit is smaller than each first mark unit. In addition, each dummy mark unit of the dummy mark pattern has a first width, each first mark unit of the first mark pattern has a second width, and the first width is smaller than half of the second width.

公开(公告)号：US20200035782A1

公开(公告)日：2020-01-30

申请号：US16116859

申请日：2018-08-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Li-Wei Feng ,  En-Chiuan Liou ,  Yu-Cheng Tung ,  Wei-Lun Hsu ,  Yu-Hsiang Hung ,  Ming-Te Wei ,  Le-Tien Jung

IPC: H01L49/02 ,  H01L27/02 ,  H01L29/94 ,  H01G4/01

Abstract: The present invention provides a semiconductor structure including a substrate including a plurality of capacitor lower electrodes, the capacitor lower electrodes are arranged in a diamond array along a first direction and a second direction respectively, the first direction and the second direction are not perpendicular to each other. A supporting structure layer contacts at least parts of the capacitor lower electrodes, wherein the supporting structure layer includes a plurality of triangular openings, and the three corners of each triangular opening are overlapped with three adjacent capacitor lower electrodes respectively.

公开(公告)号：US20190317393A1

公开(公告)日：2019-10-17

申请号：US15978215

申请日：2018-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun ,  Yu-Cheng Tung ,  Sheng-Yuan Hsueh

IPC: G03F1/36 ,  G06F17/50

Abstract: A mask includes a substrate, a main pattern, a first assist pattern, and a second assist pattern. The main pattern is disposed on the substrate. The main pattern includes a first pattern and second patterns. Two of the second patterns are disposed at two opposite sides of the first pattern in a first direction. The first assist pattern is disposed on the substrate and disposed in the main pattern. The second assist pattern is disposed on the substrate and disposed outside the main pattern. The first assist pattern disposed in the main pattern may be used to improve the pattern transferring performance in a photolithography process using the mask.

公开(公告)号：US20190229024A1

公开(公告)日：2019-07-25

申请号：US16368795

申请日：2019-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/66 ,  G03F7/20 ,  H01L23/544

CPC classification number: H01L22/12 ,  G03F7/70633 ,  G03F7/70683 ,  H01L22/30 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: The present invention provides an overlay mark, including a substrate and plural sets of first pattern block and second pattern block. A first direction and a second direction are defined on the substrate, wherein the first direction and the second direction are perpendicular to each other. In each set, the first pattern block is rotational symmetrical to the second pattern block. Each first pattern block includes a big frame and plural small frame. Each second pattern block includes a big frame and plural small frame. The width of the big frame is greater than three times of the width of the small frame. The present invention further provides a method for evaluating the stability of a semiconductor manufacturing process.

公开(公告)号：US10354876B1

公开(公告)日：2019-07-16

申请号：US16016647

申请日：2018-06-24

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee ,  Ying-Chih Lin

IPC: H01L21/033 ,  H01L27/108

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate and a material layer. The substrate has a first region, and the material layer is disposed on the substrate. The material layer includes plural of first patterns and plural of second patterns arranged in an array, and two third patterns. The first patterns are disposed within the first region, the second patterns are disposed at two opposite outer sides of the first region, and the third patterns are disposed at another two opposite outer sides of the first region, wherein each of the third patterns partially merges each of a part of the first patterns and each of a part of the second patterns.

公开(公告)号：US10347716B2

公开(公告)日：2019-07-09

申请号：US15786611

申请日：2017-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chun-Yuan Wu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/308 ,  H01L21/311 ,  H01L21/283

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.

公开(公告)号：US10340381B2

公开(公告)日：2019-07-02

申请号：US16180033

申请日：2018-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: The present invention provides a method for fabricating a semiconductor structure, the method at least comprises: firstly, a substrate is provided, a dielectric layer is formed on the substrate, a gate conductive layer and two spacers are formed and disposed in the dielectric layer, wherein the two spacers are respectively disposed on both sides of the gate conductive layer, next, parts of the gate conductive layer are removed, and parts of the two spacers are removed, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and afterwards, a stress cap layer is then formed, overlying the gate conductive layer and the two spacers, wherein parts of the stress cap layer is located right above the two spacers.

公开(公告)号：US10332877B2

公开(公告)日：2019-06-25

申请号：US15242591

申请日：2016-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L21/8234

Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A gate material layer is formed on the semiconductor substrate, and the fin structure is covered by the gate material layer. A trench is formed partly in the gate material layer and partly in the fin structure. An isolation structure is formed partly in the trench and partly outside the trench. At least one gate structure is formed straddling the fin structure by patterning the gate material layer after the step of forming the isolation structure. A top surface of the isolation structure is higher than a top surface of the gate structure in a vertical direction for enhancing the isolation performance of the isolation structure. A sidewall spacer is formed on sidewalls of the isolation structure, and there is no gate structure formed on the isolation structure.

公开(公告)号：US10283616B2

公开(公告)日：2019-05-07

申请号：US15252200

申请日：2016-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L29/78

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.