公开(公告)号：US07269080B2

公开(公告)日：2007-09-11

申请号：US11195359

申请日：2005-08-02

申请人： Ferdinando Bedeschi ,  Claudio Resta

发明人： Ferdinando Bedeschi ,  Claudio Resta

IPC分类号： G11C5/14

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/009

摘要： A nonvolatile phase change memory device including a memory array formed by memory cells arranged in rows and columns, word lines connected to first terminals of memory cells arranged on the same row, and bit lines connected to second terminals of memory cells arranged on the same column; a row decoder coupled to the memory array to bias the word lines; a column decoder coupled to the memory array to bias the bit lines; and a biasing circuit coupled to the row decoder and to the column decoder to supply a first biasing voltage and a second biasing voltage to the terminals of an addressed memory cell, wherein the first biasing voltage is a positive biasing voltage and the second biasing voltage is a negative biasing voltage.

摘要翻译： 一种非易失性相变存储器件，包括由排列成行和列的存储单元形成的存储器阵列，连接到布置在同一行上的存储器单元的第一端子的字线，以及连接到布置在同一列上的存储器单元的第二端子的位线 ; 耦合到所述存储器阵列以偏置所述字线的行解码器; 耦合到存储器阵列以偏置位线的列解码器; 以及耦合到行解码器和列解码器的偏置电路，以向寻址的存储器单元的端子提供第一偏置电压和第二偏置电压，其中第一偏置电压是正偏压，而第二偏压是 负偏压电压。

公开(公告)号：US20060221678A1

公开(公告)日：2006-10-05

申请号：US11093879

申请日：2005-03-30

申请人： Ferdinando Bedeschi ,  Claudio Resta

发明人： Ferdinando Bedeschi ,  Claudio Resta

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5645 ,  G11C2213/79

摘要： A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

摘要翻译： 一种用于读取适于存储逻辑值的至少一个存储单元的读取电路，所述至少一个存储单元包括：由相变材料制成的存储元件; 以及用于响应于所述存储单元的选择将所述存储元件耦合到所述读取电路的访问元件，所述读取电路包括：用于向所述至少一个存储器单元提供感测电流的感测电流供应装置; 以及至少一个读出放大器，用于基于在其上形成的电压来确定存储在存储器单元中的逻辑值，所述至少一个读出放大器包括用于限制存储器单元两端的电压的电压限制电路，用于保存所存储的逻辑值 其中所述电压限制电路包括用于吸收钳位电流的电流沉降片，其从所述感测电流中减去并且取决于所存储的逻辑值。

公开(公告)号：US07092277B2

公开(公告)日：2006-08-15

申请号：US10926784

申请日：2004-08-25

申请人： Ferdinando Bedeschi ,  Claudio Resta

发明人： Ferdinando Bedeschi ,  Claudio Resta

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/79

摘要： A memory device is proposed. The memory device includes a matrix of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell including a functional element with a programmable resistivity and a unidirectional conduction access element connected in series, a plurality of word lines and a plurality of bit lines, the memory cells of each row being connected to a corresponding word line and the memory cells of each column being connected to a corresponding bit line, means for driving the bit lines to a desired voltage, means for selecting at least one bit line in an operative condition of the memory device, each selected bit line being connected to the means for driving and each deselected bit line being disconnected from the means for driving, and means for selecting a word line in the operative condition, each access element associated with the selected word line and the at least one selected bit line being forward biased and the other access elements being reverse biased; the memory device further includes means for biasing the deselected bit lines in the operative condition to prevent a leakage current of the reverse biased access elements from forward biasing the access elements associated with the selected word line and the deselected bit lines.

摘要翻译： 提出了一种存储器件。 存储器件包括布置成多行和多列的存储器单元矩阵，每个存储单元包括具有可编程电阻率的功能元件和串联连接的单向导通存取元件，多个字线和多个 每行的存储单元连接到对应的字线，并且每列的存储单元连接到对应的位线，用于将位线驱动到期望电压的装置，用于选择至少一个位的装置 在存储器件的操作状态下，每个选定的位线连接到用于驱动的​​装置，并且每个取消选择的位线与用于驱动的​​装置断开，以及用于在操作状态中选择字线的装置，每个存取元件相关联 与所选择的字线和所述至少一个所选择的位线被正向偏置，并且其他存取元件被反向偏置; 存储器件还包括用于在操作状态下偏置未选择的位线的装置，以防止反向偏置的存取元件的泄漏电流向前偏置与所选择的字线和取消选择的位线相关联的存取元件。

公开(公告)号：US20060067154A1

公开(公告)日：2006-03-30

申请号：US10948885

申请日：2004-09-24

申请人： Ferdinando Bedeschi ,  Claudio Resta

发明人： Ferdinando Bedeschi ,  Claudio Resta

IPC分类号： G11C8/00

CPC分类号： G11C8/08

摘要： A biasing circuit for use in a non-volatile memory device is coupled to the row decoder and to the column decoder to supply a first and at least a second biasing voltage for the word and bit lines, and includes a first voltage booster having a first input coupled to receive a supply voltage, a second input coupled to receive a reference voltage, and an output coupled to one of the row decoder and the column decoder to supply the first biasing voltage. A second voltage booster has a first input coupled to receive the supply voltage, a second input coupled to the output of the first voltage booster to receive the first biasing voltage, and an output coupled to the other of the row decoder and the column decoder to supply the second biasing voltage.

公开(公告)号：US20060056265A1

公开(公告)日：2006-03-16

申请号：US11195359

申请日：2005-08-02

申请人： Ferdinando Bedeschi ,  Claudio Resta

发明人： Ferdinando Bedeschi ,  Claudio Resta

IPC分类号： G11C8/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/009

摘要： A nonvolatile phase change memory device including a memory array formed by memory cells arranged in rows and columns, word lines connected to first terminals of memory cells arranged on the same row, and bit lines connected to second terminals of memory cells arranged on the same column; a row decoder coupled to the memory array to bias the word lines; a column decoder coupled to the memory array to bias the bit lines; and a biasing circuit coupled to the row decoder and to the column decoder to supply a first biasing voltage and a second biasing voltage to the terminals of an addressed memory cell, wherein the first biasing voltage is a positive biasing voltage and the second biasing voltage is a negative biasing voltage.

摘要翻译： 一种非易失性相变存储器件，包括由排列成行和列的存储单元形成的存储器阵列，连接到布置在同一行上的存储器单元的第一端子的字线，以及连接到布置在同一列上的存储器单元的第二端子的位线 ; 耦合到存储器阵列以偏置字线的行解码器; 耦合到存储器阵列以偏置位线的列解码器; 以及耦合到行解码器和列解码器的偏置电路，以向寻址的存储器单元的端子提供第一偏置电压和第二偏置电压，其中第一偏置电压是正偏压，而第二偏压是 负偏压电压。

公开(公告)号：US08565031B2

公开(公告)日：2013-10-22

申请号：US13561172

申请日：2012-07-30

申请人： Ferdinando Bedeschi ,  Claudio Resta

发明人： Ferdinando Bedeschi ,  Claudio Resta

IPC分类号： G11C7/06

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5645 ,  G11C2213/79

摘要： A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

摘要翻译： 一种用于读取适于存储逻辑值的至少一个存储单元的读取电路，所述至少一个存储单元包括：由相变材料制成的存储元件; 以及用于响应于所述存储单元的选择将所述存储元件耦合到所述读取电路的访问元件，所述读取电路包括：用于向所述至少一个存储器单元提供感测电流的感测电流供应装置; 以及至少一个读出放大器，用于基于在其上形成的电压来确定存储在存储器单元中的逻辑值，所述至少一个读出放大器包括用于限制存储器单元两端的电压的电压限制电路，用于保存所存储的逻辑值 其中所述电压限制电路包括用于吸收钳位电流的电流沉降片，其从所述感测电流中减去并且取决于所存储的逻辑值。

公开(公告)号：US08026757B2

公开(公告)日：2011-09-27

申请号：US12570770

申请日：2009-09-30

申请人： Ferdinando Bedeschi ,  Claudio Resta

发明人： Ferdinando Bedeschi ,  Claudio Resta

IPC分类号： G11C11/4074 ,  H03K17/687 ,  G05F3/26

CPC分类号： G05F3/26

摘要： A current mirror circuit is provided with a first current mirror including first and second mirror transistors sharing a common control terminal; the first mirror transistor has a conduction terminal for receiving, during a first operating condition, a first reference current, and the second mirror transistor has a respective conduction terminal for providing, during the first operating condition, a mirrored current based on the first reference current. The current mirror circuit is provided with a switching stage operable to connect the control terminal to the conduction terminal of the first mirror transistor during the first operating condition, and to disconnect the control terminal from the same conduction terminal of the first mirror transistor, and either letting it substantially float or connecting it to a reference voltage, during a second operating condition, in particular a condition of stand-by.

摘要翻译： 电流镜电路设置有第一电流镜，其包括共享公共控制端的第一和第二镜像晶体管; 第一反射镜晶体管具有用于在第一操作条件期间接收第一参考电流的导电端子，并且第二反射镜晶体管具有相应的导通端子，用于在第一操作条件期间提供基于第一参考电流的镜像电流 。 电流镜电路设置有开关级，可操作以在第一操作状态期间将控制端连接到第一镜晶体管的导通端，并且将控制端与第一镜晶体管的相同导通端断开， 在第二操作条件下，特别是待机状态，使其基本上浮动或将其连接到参考电压。

公开(公告)号：US07869267B2

公开(公告)日：2011-01-11

申请号：US12345411

申请日：2008-12-29

申请人： Claudio Resta ,  Ferdinando Bedeschi

发明人： Claudio Resta ,  Ferdinando Bedeschi

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C8/10 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2213/79

摘要： A method for accessing a phase change memory device, wherein a first sub-plurality of bitlines is grouped in a first group and a second sub-plurality of bitlines is grouped in a second group. At least a bitline in the first and second groups are selected; currents are supplied to the selected bitlines; and a selected wordline is biased. The bitlines are selected by selecting a first bitline in the first group and, while the first bitline is selected, selecting a second bitline in the second group which is arranged on the selected wordline symmetrically to the first bitline in the first group.

摘要翻译： 一种用于访问相变存储器件的方法，其中第一组多个位线被分组在第一组中，并且第二副多个位线被分组在第二组中。 至少选择第一和第二组的位线; 电流被提供给选定的位线; 并且选定的字线有偏见。 通过选择第一组中的第一位线来选择位线，并且在选择第一位线的同时，在第二组中选择布置在所选择的字线上的与第一组中的第一位线对称的第二位线。

公开(公告)号：US07570524B2

公开(公告)日：2009-08-04

申请号：US11093879

申请日：2005-03-30

申请人： Ferdinando Bedeschi ,  Claudio Resta

发明人： Ferdinando Bedeschi ,  Claudio Resta

IPC分类号： G11C7/08

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5645 ,  G11C2213/79

摘要： A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.

摘要翻译： 一种用于读取适于存储逻辑值的至少一个存储单元的读取电路，所述至少一个存储单元包括：由相变材料制成的存储元件; 以及用于响应于所述存储单元的选择将所述存储元件耦合到所述读取电路的访问元件，所述读取电路包括：用于向所述至少一个存储器单元提供感测电流的感测电流供应装置; 以及至少一个读出放大器，用于基于在其上形成的电压来确定存储在存储器单元中的逻辑值，所述至少一个读出放大器包括用于限制存储器单元两端的电压的电压限制电路，用于保存所存储的逻辑值 其中所述电压限制电路包括用于吸收钳位电流的电流沉降片，其从所述感测电流中减去并且取决于所存储的逻辑值。

公开(公告)号：US07203087B2

公开(公告)日：2007-04-10

申请号：US11018550

申请日：2004-12-20

申请人： Claudio Resta ,  Ferdinando Bedeschi ,  Guido Torelli

发明人： Claudio Resta ,  Ferdinando Bedeschi ,  Guido Torelli

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C7/12 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004

摘要： A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals connected to a same bit line and memory cells arranged on the same row having respective second terminals selectively connectable to a same word line; a supply line providing a supply voltage; a column addressing circuit and a row addressing circuit for respectively addressing a bit line and a word line corresponding to a memory cell selected for reading in the reading configuration. The column addressing circuit is configured to bias the addressed bit line corresponding to the selected memory cell substantially at the supply voltage in the reading configuration. A row driving circuit biases the addressed word line corresponding to the selected memory cell at a non-zero word line read voltage, so that a predetermined cell voltage, lower than a phase change voltage, is applied between the first terminal and the second terminal of the selected memory cell in the reading configuration.

摘要翻译： 一种存储器件，具有读取配置，并且包括排列成行和列的多个存储器单元，布置在同一列上的存储器单元具有连接到相同位线的相应第一端子和布置在同一行上的存储器单元，该存储单元具有相应的第二端子 可选择性地连接到相同的字线; 提供电源电压的电源线; 列寻址电路和行寻址电路，用于分别寻址与读取配置中读取的存储单元对应的位线和字线。 列寻址电路被配置为在读取配置中基本上以电源电压偏置对应于所选存储单元的寻址位线。 行驱动电路以非零字线读取电压偏置对应于所选存储单元的寻址字线，使得在第一端和第二端之间施加低于相变电压的预定电池电压 读取配置中选定的存储单元。