Abstract:
A physical coding sublayer (PCS) device in a physical layer device of an Ethernet network device includes a multiplexer that aggregates data, which includes at least one of data portions and control portions, from a plurality of data streams into a multiplexed data block. An encoder encodes the multiplexed data block to produce an encoded data block that includes n data blocks. Each of the n data blocks includes at least one of data portions, pointer portions, and control code portions. The control code portions can be located within any of the n data blocks.
Abstract:
A cable tester comprises a test initiating module that performs B cable tests. Each of said B cable tests includes selectively transmitting a test pulse on the cable, measuring a reflection amplitude, and calculating a cable length. A test results module determines a cable status for each of said B cable tests based on said measured amplitude and said calculated cable length and that determines an overall cable status of the cable based on the cable at least one of passing and failing A out of B cable tests. A and B are integers greater than zero and B is greater than A.
Abstract:
A physical layer device for a network device comprises a converter module that selectively converts an n-bit input to an m-bit output based on first and second mapping functions. A scrambler module selectively scrambles the m-bit output. An encoding module receives the m-bit output from the scrambler module and selectively maps the m-bit output based on the first mapping function to three level output signals and the m-bit output based on the second mapping function to four level output signals.
Abstract:
A system for encoding signals for a network device includes an encoder configured to encode a transmit control signal. The transmit control signal includes a transmit enable signal in a first half of a cycle of a clock signal, and a transmit error signal in a second half of the cycle of the clock signal. The system includes a control signal transmitter configured to transmit the encoded transmit control signal. The system includes a data signal transmitter configured to transmit a transmit data signal. When neither the transmit enable signal nor the transmit error signal is in a first state in a respective half of the cycle of the clock signal, the transmit data signal includes signaling data.
Abstract:
A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the analysis may further involve obtaining a likelihood that the correlated photons were emitted by a transistor. After correlation, the analysis may also further involve assigning a weight to individual photon emissions as a function of the correlation. The weight, in some instances, reflecting a likelihood that the photons were emitted by a transistor. The analysis may further involve automatically identifying transistors in a photon emission image.
Abstract:
An energy saving circuit is connected to a receiver of a first physical layer of a first network device. The energy saving device has first and second energy saving modes. In the first energy saving mode, a sense circuit generates a receive signal when connection activity is detected by the receiver. The energy saving circuit powers down the physical layer when the receiver does not detect the connection activity. An autonegotiation circuit powers up the first physical layer and negotiates a connection with a second physical layer of a second network device when the sense circuit generates the receive signal. In a second energy saving mode, a second timer periodically powers a transmitter and generates a link pulse. After the transmitter generates the link pulse, the transmitter is turned off.
Abstract:
A cable tester tests cable and determines a cable pass/fail status. A pretest module senses activity on the cable and selectively enables testing based on the sensed activity. A test module is enabled by the pretest module, transmits a test pulse on the cable, measures a reflection amplitude, and calculates a cable length. The cable status includes an open status, a short status, and a normal status. The test module determines the cable status of the cable based on the cable at least one of passing and failing A out of B cable tests. The test module determines the cable status for each of the B tests based on the measured amplitude and the calculated cable length.
Abstract:
An arrangement for secure repeater communication in an IEEE 802.3 network by transmitting transmit data and a transmit enable signal on a selected repeater port based on an address lookup table in the repeater core. The other repeater ports that do not have a network address corresponding to the destination address of data packet receive corrupted data generated in response to signals from the respective repeater ports. The repeater ports cause generation of corrupted data by concurrently outputting an asserted transmit error signal and an unasserted transmit enable signal on the corresponding media independent interface. A physical layer transceiver, upon detecting the concurrent assertion of the transmit error signal and the deassertion of the transmit enable signal on the media independent interface, selectively outputs a prescribed data pattern as the transmit data to the network node. The prescribed data pattern may also be output to a secondary media independent interface, which receives a modified transmit enable signal. Hence, network nodes receiving the corrupted transmit data interpret the corrupted transmit data as a valid data packet for another network node, as opposed to symbol errors. Hence, network data can be transmitted along secure repeater ports without generation of an artificially high number of symbol errors.
Abstract:
A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.
Abstract:
A transmitter within a line driver circuit is configured to supply data signals in compliance with the Multilevel Transmission-3 (MLT-3) protocol for high speed data communication. The transmitter comprises a pre-driver system and a final driver. The pre-driver system comprises a plurality of individual pre-drivers that are in parallel. A zero drive logic designates any number of individual pre-drivers as zero drive types, such that these designated zero drive pre-drivers are turned ON during a zero signaling state. The partially turned ON pre-driver system, during the zero state, permits the final driver to rapidly output positive and negative signals in accord with the MLT-3 protocol.