公开(公告)号：US20100025777A1

公开(公告)日：2010-02-04

申请号：US12577022

申请日：2009-10-09

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： H01L29/78

CPC分类号： H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/7848

摘要： A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.

摘要翻译： 一种用于抑制在晶格中的掺杂剂注入之后的晶格中的渗漏促进缺陷的形成的方法。 该方法提供原子的压缩层，这些原子的尺寸大于晶格构件原子的尺寸。 然后将晶格退火足以使间隙缺陷原子从压缩层发射的时间，并且以这种方式，在离压缩层一定距离处的晶格中形成能量稳定的缺陷。

公开(公告)号：US20090236673A1

公开(公告)日：2009-09-24

申请号：US12464211

申请日：2009-05-12

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： H01L27/088 ,  H01L29/78

CPC分类号： H01L21/823412 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/7833

摘要： A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout

摘要翻译： 一种用于平滑集成电路布局中阈值电压变化的方法。 该方法开始于识别与布局中的晶体管相关联的重组表面。 处理这种复合表面以影响与这些表面相邻的间隙原子的重组，从而最小化布局内的晶体管的阈值电压的变化

公开(公告)号：US20090108408A1

公开(公告)日：2009-04-30

申请号：US11926485

申请日：2007-10-29

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： H01L21/322 ,  H01L29/32

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/3221 ,  H01L21/324

摘要： A method for minimizing the effects of defects produced in a implantated area of a crystal lattice during dopant implantation in the lattice. The method begins with the step of implanting a trap layer of trap atoms, the trap atoms having a size less than that of the lattice member atoms. After implantation, the lattice is annealed for a time sufficient for interstitial defect atoms to be emitted from the defect area. In that manner, energetically stable pairs are formed between trap atoms and emitted interstitial atoms.

摘要翻译： 一种用于最小化在晶格中的掺杂剂注入期间在晶格的注入区域中产生的缺陷的影响的方法。 该方法开始于注入陷阱原子的捕获层的步骤，陷阱原子的尺寸小于晶格构件原子的尺寸。 植入后，晶格退火足以使间隙缺陷原子从缺陷区域发射的时间。 以这种方式，在陷阱原子和发射的间隙原子之间形成能量稳定的对。

公开(公告)号：US20090108293A1

公开(公告)日：2009-04-30

申请号：US11928142

申请日：2007-10-30

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： H01L29/778 ,  H01L21/225

CPC分类号： H01L21/324 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/7848

摘要： A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.

摘要翻译： 一种用于抑制在晶格中的掺杂剂注入之后的晶格中的渗漏促进缺陷的形成的方法。 该方法提供原子的压缩层，这些原子的尺寸大于晶格构件原子的尺寸。 然后将晶格退火足以使间隙缺陷原子从压缩层发射的时间，并且以这种方式，在离压缩层一定距离处的晶格中形成能量稳定的缺陷。

公开(公告)号：US20070246776A1

公开(公告)日：2007-10-25

申请号：US11379548

申请日：2006-04-20

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： H01L27/12

CPC分类号： H01L21/823807 ,  H01L21/7624 ,  H01L29/7843

摘要： Improved layouts take better advantage of desirable cap-layer induced transverse and vertical stress. In one aspect, roughly described, a tensile strained cap material overlies the transistor channels in the N-channel diffusion regions but not the P-channel diffusion regions. The material terminates at an edge that is located as far as practical from the N-channel diffusion, toward the P-channel diffusion. In another aspect, roughly described, a gate conductor crosses a P-channel diffusion region and terminates as far as practical beyond the edge without making undesirable electrical contact with any other features of the integrated circuit design, and without overlying any other diffusion regions. A compressively strained cap layer overlies the P-channel diffusion. In yet another aspect, roughly described, a gate conductor crosses an N-channel diffusion and extends by as short a distance as practical before terminating or turning. A tensile strained cap material overlies the N-channel diffusion.

摘要翻译： 改进的布局更好地利用所需的帽层诱导的横向和垂直应力。 在一个方面，粗略地描述，拉伸应变帽材料覆盖在N沟道扩散区域中的晶体管沟道上，但不覆盖P沟道扩散区域。 该材料终止于从N沟道扩散尽可能远地朝向P沟道扩散的边缘。 在另一方面，粗略地描述，栅极导体穿过P沟道扩散区域并且尽可能远地超过边缘终止，而不会与集成电路设计的任何其它特征产生不期望的电接触，并且不覆盖任何其它扩散区域。 压缩应变盖层覆盖P沟道扩散。 在另一方面，粗略地描述，栅极导体穿过N沟道扩散并在终止或转动之前延伸尽可能短的距离。 拉伸应变盖材料覆盖在N沟道扩散层上。

公开(公告)号：US08762924B2

公开(公告)日：2014-06-24

申请号：US12510188

申请日：2009-07-27

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

摘要翻译： 粗略地描述了一种用于近似集成电路布局中的沟道区域中的应力诱导迁移率增强的方法，包括近似在通道中的多个采样点中的每一个处的应力，将每个采样点处的应力近似转换为 相应的移动性增强值，并在所有采样点平均移动性增强值。 该方法实现了集成电路应力分析，其考虑了由多个应力产生机制所产生的应力，具有沿通道长度以外的矢量分量的应力，以及由于在邻域中存在其它结构的应力贡献（包括缓解） 正在研究的频道区域，除了最接近的STI接口。 该方法还能够对大型布局区域甚至全芯片布局进行应力分析，而不会导致完整TCAD仿真的计算成本。

公开(公告)号：US08713510B2

公开(公告)日：2014-04-29

申请号：US12510185

申请日：2009-07-27

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

公开(公告)号：US08407634B1

公开(公告)日：2013-03-26

申请号：US11291294

申请日：2005-12-01

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F9/45

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

公开(公告)号：US07691693B2

公开(公告)日：2010-04-06

申请号：US11757294

申请日：2007-06-01

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： H01L21/338

CPC分类号： H01L21/823412 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/7833

摘要： A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of interstitial atoms adjacent such surfaces, thus minimizing variations in threshold voltage of transistors within the layout.

摘要翻译： 一种用于平滑集成电路布局中阈值电压变化的方法。 该方法开始于识别与布局中的晶体管相关联的重组表面。 处理这种复合表面以影响与这些表面相邻的间隙原子的重组，从而最小化布局内晶体管的阈值电压的变化。

公开(公告)号：US20100023902A1

公开(公告)日：2010-01-28

申请号：US12510190

申请日：2009-07-27

申请人： Victor Moroz ,  Dipankar Pramanik

发明人： Victor Moroz ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5022 ,  G06F17/5081

摘要： Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.