公开(公告)号：US07606306B2

公开(公告)日：2009-10-20

申请号：US10907441

申请日：2005-04-01

申请人： Ying-Chih Yang ,  Tsung-Hsien Lin ,  Jen-Yi Liao

发明人： Ying-Chih Yang ,  Tsung-Hsien Lin ,  Jen-Yi Liao

IPC分类号： H04N7/12

CPC分类号： H04N5/21 ,  H04N5/4401 ,  H04N19/117 ,  H04N19/159 ,  H04N19/172 ,  H04N19/44 ,  H04N19/61 ,  H04N21/440218 ,  H04N21/4621

摘要： An output method for improving video image quality is provided. First, a frame data of a first frame is received, wherein the first frame may coincide with a first type or a second type. Thereafter, the first frame is subjected to a signal process step to output a processed first frame with a first standard, wherein the processed first frame comprises a first signal to noise (S/N) ratio. Next, a frame data of a second frame with a second standard is received, wherein the second frame coincides with a third type. Thereafter, a first decompression process of frame data is performed on the second frame to output a processed second frame with the first standard, wherein the processed second frame comprises a second S/N ratio. In addition, a difference between the first S/N ratio and the second S/N ratio is smaller than a predetermined minimum tolerance.

摘要翻译： 提供了一种用于提高视频图像质量的输出方法。 首先，接收第一帧的帧数据，其中第一帧可以与第一类型或第二类型重合。 此后，对第一帧进行信号处理步骤以输出具有第一标准的经处理的第一帧，其中处理的第一帧包括第一信噪比（S / N）比。 接下来，接收具有第二标准的第二帧的帧数据，其中第二帧与第三类型重合。 此后，对第二帧执行帧数据的第一解压缩处理，以输出具有第一标准的经处理的第二帧，其中处理后的第二帧包括第二S / N比。 此外，第一S / N比和第二S / N比之间的差小于预定的最小容差。

公开(公告)号：US07289782B2

公开(公告)日：2007-10-30

申请号：US11222632

申请日：2005-09-09

申请人： Tsung-Hsien Lin ,  Hung-Ming Chien

发明人： Tsung-Hsien Lin ,  Hung-Ming Chien

IPC分类号： H04B1/06

CPC分类号： H03L7/1976 ,  H03L7/0891 ,  H04W84/042 ,  H04W84/18 ,  H04W88/02

摘要： A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

摘要翻译： 线性化振荡合成器包括相位和频率检测模块，电荷泵电路，低通滤波器，压控振荡器和反馈模块。 相位和频率检测模块可操作地耦合以产生基于参考振荡和反馈振荡之间的相位和/或频率差的充电信号，降压信号和截止信号。 参考振荡由诸如晶体振荡器的时钟源产生，而分频器模块通过将输出振荡除以分频值来产生反馈振荡。 电荷泵电路响应于充电信号产生正电流，响应于降压信号产生负电流并且还产生非零偏移电流。 非零偏移电流将电荷泵的稳态工作状态和其他工作条件移动到电荷泵性能曲线的线性区域。

公开(公告)号：US07099643B2

公开(公告)日：2006-08-29

申请号：US10445536

申请日：2003-05-27

申请人： Tsung-Hsien Lin

发明人： Tsung-Hsien Lin

IPC分类号： H04B1/16 ,  H04B7/20

CPC分类号： H03L7/097 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/113 ,  H03L7/187

摘要： An analog open-loop voltage controlled oscillator (VCO) calibration circuit and method for selecting the frequency of the VCO for a phase locked loop (PLL).A frequency divider module produces a 50% duty cycle divided local oscillation and a 50% duty cycle divided reference signal, wherein the divided signals are substantially equal. A period-to-voltage conversion module converts the divided local oscillation signal and the divided reference signal to voltages proportional to the divided signals. A comparator module produces a frequency adjustment signal based on a comparison of the proportional voltages and couples the frequency adjustment signal to a logic module which produces a frequency compensation signal based on the frequency adjustment signal. The frequency compensation signal functions to adjust the configuration of switched capacitors in a capacitor bank, coupled to the VCO tuned circuit, until the divided local oscillation signal is substantially equal to the divided reference signal.

摘要翻译： 一种模拟开环压控振荡器（VCO）校准电路和用于选择VCO的频率用于锁相环（PLL）的方法。 分频器模块产生50％占空比分频本地振荡和50％占空比分频参考信号，其中分频信号基本相等。 周期电压转换模块将分频的本地振荡信号和划分的参考信号转换成与分频信号成比例的电压。 比较器模块基于比例电压的比较产生频率调整信号，并将频率调整信号耦合到基于频率调整信号产生频率补偿信号的逻辑模块。 频率补偿信号用于调整耦合到VCO调谐电路的电容器组中的开关电容器的配置，直到分频的本地振荡信号基本上等于分频的参考信号。

公开(公告)号：US20060078045A1

公开(公告)日：2006-04-13

申请号：US10907441

申请日：2005-04-01

申请人： Ying-Chih Yang ,  Tsung-Hsien Lin ,  Jen-Yi Liao

发明人： Ying-Chih Yang ,  Tsung-Hsien Lin ,  Jen-Yi Liao

IPC分类号： H04N7/12

CPC分类号： H04N5/21 ,  H04N5/4401 ,  H04N19/117 ,  H04N19/159 ,  H04N19/172 ,  H04N19/44 ,  H04N19/61 ,  H04N21/440218 ,  H04N21/4621

摘要： An output method for improving video image quality is provided. First, a frame data of a first frame is received, wherein the first frame may coincide with a first type or a second type. Thereafter, the first frame is subjected to a signal process step to output a processed first frame with a first standard, wherein the processed first frame comprises a first signal to noise (S/N) ratio. Next, a frame data of a second frame with a second standard is received, wherein the second frame coincides with a third type. Thereafter, a first decompression process of frame data is performed on the second frame to output a processed second frame with the first standard, wherein the processed second frame comprises a second S/N ratio. In addition, a difference between the first S/N ratio and the second S/N ratio is smaller than a predetermined minimum tolerance.

摘要翻译： 提供了一种用于提高视频图像质量的输出方法。 首先，接收第一帧的帧数据，其中第一帧可以与第一类型或第二类型重合。 此后，对第一帧进行信号处理步骤以输出具有第一标准的经处理的第一帧，其中处理的第一帧包括第一信噪比（S / N）比。 接下来，接收具有第二标准的第二帧的帧数据，其中第二帧与第三类型重合。 此后，对第二帧执行帧数据的第一解压缩处理，以输出具有第一标准的经处理的第二帧，其中处理后的第二帧包括第二S / N比。 此外，第一S / N比和第二S / N比之间的差小于预定的最小容差。

公开(公告)号：US06998877B2

公开(公告)日：2006-02-14

申请号：US10842608

申请日：2004-05-10

申请人： Tsung-Hsien Lin

发明人： Tsung-Hsien Lin

IPC分类号： H03K19/20

CPC分类号： H03K19/09432

摘要： A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output. The 2nd load is coupled to the drain of the complimentary transistor to provide a 2nd phase of the differential logic output.

摘要翻译： 一个高速差分信号逻辑门包括一个输入晶体管，第二输入晶体管，互补晶体管，电流源，第一输入晶体管，第二输入晶体管， 负载和2 负载。 第一输入晶体管可操作地耦合以接收第一差分输入信号的第一输入逻辑信号，其可以是第一差分输入信号的一相。 第二输入晶体管与第一输入晶体管并联耦合，并进一步耦合以接收第二输入逻辑信号，其中， 可以是差分输入信号的2相。 互补晶体管可操作地耦合到第一和第二和第二输入晶体管的源极并且接收互补输入信号，其模拟1 相位差分逻辑输出。 二极管负载耦合到互补晶体管的漏极以提供差分逻辑输出的第二相。

公开(公告)号：US06990143B2

公开(公告)日：2006-01-24

申请号：US10132856

申请日：2002-04-25

申请人： Tsung-Hsien Lin

发明人： Tsung-Hsien Lin

IPC分类号： H04B17/00 ,  H04B3/46 ,  H04Q1/20

CPC分类号： H03K5/1565 ,  H03L7/0812

摘要： A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a controllable delay module, a duty cycle control loop module and a reset circuit. The edge generator is coupled to generate a clean edge of the reference clock. The controllable delay module is coupled to produce a delayed edge from the clean edge based on a duty cycle control signal. The duty cycle control loop module is coupled to generate the duty cycle control signal based on the delayed edge and the reference clock signals. The reset circuit is coupled to reset the edge generator to produce a second edge. The second edge is delayed by the controllable delay module to produce a second delayed edge such that the delayed edge and the second delayed edge constitute one period of the fifty percent duty cycle clock.

摘要翻译： 一种用于从参考时钟产生五十％占空比时钟的方法和装置。 该方法和装置包括边缘发生器，可控延迟模块，占空比控制环模块和复位电路。 边缘发生器被耦合以产生参考时钟的干净边缘。 可控延迟模块被耦合以基于占空比控制信号从干净边缘产生延迟边缘。 占空比控制环模块被耦合以基于延迟边沿和参考时钟信号产生占空比控制信号。 复位电路被耦合以复位边缘发生器以产生第二边缘。 第二边缘被可控延迟模块延迟以产生第二延迟边缘，使得延迟边缘和第二延迟边缘构成百分之五十占空比时钟的一个周期。

公开(公告)号：US06980789B2

公开(公告)日：2005-12-27

申请号：US10958916

申请日：2004-10-05

申请人： Tsung-Hsien Lin

发明人： Tsung-Hsien Lin

IPC分类号： H03K17/041 ,  H03K23/66 ,  H03L7/18 ,  H03L7/197 ,  H03K3/289

CPC分类号： H03L7/18 ,  H03K17/04106 ,  H03K23/667 ,  H03L7/1976

摘要： A divider module for use in an oscillation synthesizer includes a plurality of flip-flops and a logic circuit. The plurality of flip-flops is interoperably coupled to produce a divider value based on a control signal. The logic circuit is operably coupled to produce the control signal based on divider select signals. Each of the plurality of flip-flops includes a first differential latch module, a second differential latch module. The first differential latch module is operably coupled to produce a differential latched signal based on a differential flip-flop input signal. The second differential latch module is operably coupled to produce a differential flip-flop output based on the differential latched signal. Each of the first and second differential latch modules includes a sample transistor section, a hold transistor section, a first gating circuit, and a second gating circuit.

摘要翻译： 用于振荡合成器的分频器模块包括多个触发器和逻辑电路。 多个触发器可互操作地耦合以产生基于控制信号的分频值。 逻辑电路可操作地耦合以基于分频器选择信号产生控制信号。 多个触发器中的每一个包括第一差分锁存模块，第二差分锁存模块。 第一差分锁存模块可操作地耦合以产生基于差分触发器输入信号的差分锁存信号。 第二差分锁存模块可操作地耦合以产生基于差分锁存信号的差分触发器输出。 第一和第二差分锁存模块中的每一个包括采样晶体管部分，保持晶体管部分，第一选通电路和第二门控电路。

公开(公告)号：US06819915B2

公开(公告)日：2004-11-16

申请号：US10728201

申请日：2003-12-04

申请人： Tsung-Hsien Lin

发明人： Tsung-Hsien Lin

IPC分类号： H04B138

CPC分类号： H03K3/356139 ,  H03K3/0375 ,  H03K23/667

摘要： A differential latch includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation.

摘要翻译： 差分锁存器包括采样晶体管部分，保持晶体管部分，第1门控电路和第2门控电路。 当与电源电压（例如，VDD和VSS）耦合到差分输入信号时，采样晶体管部分可操作地耦合到采样。 当耦合到电源电压时，保持晶体管部分可操作地耦合到锁存器，以产生锁存的差分信号。 第一门控电路可操作以根据时钟逻辑运算和第二时钟逻辑运算将采样的晶体管部分耦合到电源电压。 第二门控电路可操作以根据3时钟逻辑运算和4时钟逻辑运算将保持晶体管部分耦合到电源电压。

公开(公告)号：US20140077192A1

公开(公告)日：2014-03-20

申请号：US14024646

申请日：2013-09-12

申请人： Tsung-Hsien Lin ,  Hen-Ta Kang ,  Chien-Chung Chen

发明人： Tsung-Hsien Lin ,  Hen-Ta Kang ,  Chien-Chung Chen

IPC分类号： H01L51/52

CPC分类号： H01L51/5262 ,  H01L51/5036 ,  H01L51/504 ,  H01L51/52 ,  H01L51/5275 ,  H01L2251/558

摘要： An organic light emitting diode (OLED) has a plurality of light emitting regions. The OLED includes an anode layer, a cathode layer, an organic light emitting layer, and a wavelength shift layer. The organic light emitting layer is disposed between the anode layer and the cathode layer and correspondingly provides the light emitting regions with a plurality of emitted lights. Here, the organic light emitting layer has a fixed thickness. The wavelength shift layer is disposed outside the organic light emitting layer, the cathode layer, and the anode layer. A wavelength range at half-peak of combination of the emitted lights is wider than a wavelength range at half-peak of one of the lights.

摘要翻译： 有机发光二极管（OLED）具有多个发光区域。 OLED包括阳极层，阴极层，有机发光层和波长移位层。 有机发光层设置在阳极层和阴极层之间，并且相应地为发光区域提供多个发光。 这里，有机发光层具有固定的厚度。 波长偏移层设置在有机发光层，阴极层和阳极层的外部。 发出的光的组合的半峰的波长范围宽于一个光的半峰的波长范围。

公开(公告)号：US08634199B2

公开(公告)日：2014-01-21

申请号：US13329237

申请日：2011-12-17

申请人： Yong-Hua Xiao ,  Tsung-Hsien Lin ,  Xin Ji

发明人： Yong-Hua Xiao ,  Tsung-Hsien Lin ,  Xin Ji

IPC分类号： H05K1/00 ,  H05K1/18 ,  H05K7/00

CPC分类号： H01R12/732 ,  G06F1/186 ,  H01R12/737

摘要： A connection device is used to mount a computer mini-card. The connection device includes a board, an edge connector formed a bottom side of the board, a socket, and a pole. The socket is mounted on a first side surface of the board to connect to the computer mini-card, and is electrically connected to the edge connector. The pole extends from the first side surface of the board to fix an end of the computer mini-card opposite to the socket.

摘要翻译： 连接装置用于安装计算机微型卡。 连接装置包括板，形成板的底侧的边缘连接器，插座和极。 插座安装在板的第一侧表面上以连接到计算机微型卡，并且电连接到边缘连接器。 杆从板的第一侧表面延伸以将计算机微型卡的端部固定在与插座相对的位置。