公开(公告)号：US12088308B1

公开(公告)日：2024-09-10

申请号：US17972739

申请日：2022-10-25

申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.

发明人： Stewart G. Kenly ,  Amar Vellanki ,  John L. Melanson

IPC分类号： H03L7/087 ,  H03L7/097 ,  H03L7/099

CPC分类号： H03L7/087 ,  H03L7/097 ,  H03L7/0992

摘要： A phase-lock loop (PLL) circuit provides continuous closed-loop operation when switching between operating modes, which may be selection between multiple oscillators, multiple power modes or frequency divider/multipliers of an local clock generator having one or more oscillator circuits, or other changes that may disrupt operation of the PLL. The PLL includes a loop filter having an input coupled to an output of a phase-frequency comparator that compares the output of the oscillator circuit to a reference and a control circuit for storing and restoring the complete state of the loop filter from the storage in response to a change of operating mode, so that a lock time of the phase-lock loop circuit is reduced when selection of one of the at least two selectable different output frequency ranges of the local clock generator is changed.

公开(公告)号：US11870447B2

公开(公告)日：2024-01-09

申请号：US17503966

申请日：2021-10-18

申请人： Mitsubishi Electric Corporation

发明人： Sho Ikeda ,  Akihito Hirai ,  Koji Tsutsumi ,  Masaomi Tsuru

IPC分类号： H03L7/081 ,  H03L7/097 ,  H03L7/099 ,  H03L7/093 ,  G06F7/501

CPC分类号： H03L7/0814 ,  G06F7/501 ,  H03L7/093 ,  H03L7/097 ,  H03L7/0998

摘要： A third signal having a phase intermediate between a first signal based on a reference signal and a second signal with a phase shifted by an element of a previous stage is generated, a signal obtained by shifting the phase of the third signal by a first phase shill amount is output as a second signal to an element of a subsequent stage, a phase difference between the third signal and a fourth signal obtained by shifting the phase of a first signal output from the element of the subsequent stage by the first phase shift amount is detected, and the first phase shift amount is controlled on the basis of the detected phase difference.

公开(公告)号：US11804842B2

公开(公告)日：2023-10-31

申请号：US17846362

申请日：2022-06-22

申请人： STMicroelectronics (Rousset) SAS

发明人： Nicolas Borrel ,  Jimmy Fort ,  Mathieu Lisart

IPC分类号： H03K5/22 ,  H03K19/003 ,  H03F3/45 ,  H03K19/00 ,  H03K19/17736 ,  H03L7/097 ,  H04L9/32

CPC分类号： H03K19/00384 ,  H03F3/45273 ,  H03F3/45488 ,  H03K19/0027 ,  H03K19/17744 ,  H03L7/097 ,  H04L9/3278 ,  H04L2209/12

摘要： A physically unclonable function device includes a set of diode-connected MOS transistors having a random distribution of respective threshold voltages. A first circuit is configured to impose, on each first transistor, a fixed respective gate voltage regardless of the value of a current flowing in this first transistor. A second circuit is configured to impose, on each second transistor, a fixed respective gate voltage regardless of the value of a current flowing in this second transistor. A current mirror stage is coupled between the first circuit and the second circuit and is configured to deliver the reference current from a sum of the currents flowing in the first transistors. A comparator is configured to deliver a signal whose level depends on a comparison between a first current obtained from a reference current based on the first transistors and a second current of the second transistors.

公开(公告)号：US20190058442A1

公开(公告)日：2019-02-21

申请号：US15959432

申请日：2018-04-23

申请人： Samsung Electronics Co., Ltd.

发明人： Gyeongseok SONG ,  Kang-jik KIM ,  Chang-kyung SEONG ,  Hyung-jun JUNG

IPC分类号： H03B5/12 ,  H03L7/099 ,  H03L7/097 ,  H03B5/04

CPC分类号： H03B5/1243 ,  H03B5/04 ,  H03B5/1212 ,  H03B5/1228 ,  H03B2200/004 ,  H03L7/097 ,  H03L7/099

摘要： An oscillator and method for operation of the oscillator are provided. The oscillator includes a control voltage generator configured to generate a control voltage based on dividing a power voltage that was received, an offset voltage generator configured to generate an offset voltage based on dividing the power voltage that was received, a phase locked loop (PLL) including a varactor circuit configured to modify a capacitance based on the control voltage and the offset voltage, and a calibration logic circuit configured to provide a selection control signal to the control voltage generator based on the oscillation signal, and configured to provide an offset control signal to the offset voltage generator based on the oscillation signal.

公开(公告)号：US09857477B2

公开(公告)日：2018-01-02

申请号：US14534289

申请日：2014-11-06

申请人： Research & Business Foundation SUNGKYUNKWAN UNIVERSITY

发明人： Seok Ho Yoon ,  Keun Hong Chae

IPC分类号： G01S19/29 ,  G01S19/30 ,  H03L7/087 ,  H04L27/227 ,  H03L7/093 ,  H03L7/097 ,  H03L7/185

CPC分类号： G01S19/29 ,  G01S19/30 ,  H03L7/087 ,  H03L7/093 ,  H03L7/097 ,  H03L7/185 ,  H04L27/2278

摘要： A method of generating a correlation function for a CBOC(6,1,1/11) signal according to the present invention includes generating a delayed signal delayed based on a phase delay, with respect to a signal pulse train of a CBOC(6,1,1/11)-modulated received signal, generating first to twelfth partial correlation functions by performing an autocorrelation operation of the received signal and the delayed signal with respect to a total time, generating a basic intermediate correlation function by performing an elimination operation on sixth and seventh partial correlation functions, acquiring first to fifth and eighth to twelfth additional intermediate correlation functions by performing an elimination operation on each of partial correlation functions, excluding the sixth and seventh partial correlation functions from the first to twelfth partial correlation functions, and a basic intermediate correlation function, and acquiring the main correlation function by simply summing the basic intermediate correlation function and the first to fifth and eighth to twelfth additional intermediate correlation functions.

公开(公告)号：US09716501B2

公开(公告)日：2017-07-25

申请号：US15059977

申请日：2016-03-03

申请人： SEIKO EPSON CORPORATION

发明人： Akira Shirao

IPC分类号： H03K3/02 ,  H03K19/0185 ,  H03L7/099 ,  H03B5/00 ,  H03B5/10 ,  H03B5/04 ,  H03L7/097 ,  H03L7/02 ,  H03L7/00 ,  H03L7/089 ,  H03K3/011 ,  H03K3/03

CPC分类号： H03K19/018521 ,  H03B5/00 ,  H03B5/04 ,  H03B5/10 ,  H03K3/011 ,  H03K3/0315 ,  H03L7/00 ,  H03L7/02 ,  H03L7/0891 ,  H03L7/097 ,  H03L7/099

摘要： A CR oscillation circuit includes inverters forming a loop for circulation of a signal, CR time constant circuits inserted into the loop for delaying the signal, each circuit having a capacitor, a plurality of resistance elements, and a transmission gate that selects an arbitrary resistance element of the plurality of resistance elements as a charge and discharge path of the capacitor, and a gate voltage generation circuit as means for outputting a gate voltage for controlling ON/OFF of each transmission gate that outputs a constant voltage in conjunction of a threshold voltage of a field-effect transistor as a gate voltage for turning ON the transmission gate.

公开(公告)号：US09602114B2

公开(公告)日：2017-03-21

申请号：US14853247

申请日：2015-09-14

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Michael Pelissier ,  Anton Korniienko ,  Mykhailo Zarudniev ,  Gèrard Scorletti ,  Olesia Mokrenko ,  Eric Blanco ,  Patrick Villard ,  Gèrard Billiot

IPC分类号： H03L7/06 ,  H03L7/097 ,  H03L7/08 ,  G06F17/50 ,  H04L7/00 ,  H03L7/099

CPC分类号： H03L7/097 ,  G06F17/5045 ,  H03L7/08 ,  H03L7/099 ,  H03L2207/50 ,  H04L7/0079

摘要： A design method for a phase-locked loop comprises: a controlled-frequency oscillator; a phase comparator, to determine a phase difference between an output signal of the controlled-frequency oscillator and a reference signal; a corrector to receive as input a signal representative of the phase difference and to generate at its output a first correction signal; at least one second corrector, to receive as input a signal representative of or affected by a phase noise of the reference signal or of the output signal of the controlled-frequency oscillator and to generate at its output a second correction signal; and a circuit for generating a slaving signal for the controlled-frequency oscillator on the basis of the first and second correction signals; the method using the H-infinity method. Method for fabricating such a loop comprising a design step implementing this method. Phase-locked loop thus obtained.

公开(公告)号：US09391626B2

公开(公告)日：2016-07-12

申请号：US14456064

申请日：2014-08-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

IPC分类号： H03L7/06 ,  H03L7/10 ,  H03L7/099 ,  H03L7/18 ,  H03L7/097 ,  H03L7/107

CPC分类号： H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

摘要： A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

摘要翻译： 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

公开(公告)号：US09379723B2

公开(公告)日：2016-06-28

申请号：US14399104

申请日：2012-05-11

申请人： Enrico Lia ,  Andreas Lauer ,  Dietmar Koether ,  Rüdiger Follmann

发明人： Enrico Lia ,  Andreas Lauer ,  Dietmar Koether ,  Rüdiger Follmann

IPC分类号： H03K3/00 ,  H03L7/197 ,  H03L7/097

CPC分类号： H03L7/1974 ,  H03L7/097

摘要： A method for generating a digital signal of tunable frequency may include generating a periodic first analog signal, determining a sign of a first difference between a value of the first analog signal and a first control value to determine sign flips, wherein the first control value is a variable value, and generating the digital signal of tunable frequency on the basis of the determined sign of the first difference, wherein the digital signal of tunable frequency is generated such that a subset of switches of the signal level are coincident with a respective sign flip of the determined sign of the first difference.

摘要翻译： 一种用于产生可调谐频率的数字信号的方法可以包括产生周期性的第一模拟信号，确定第一模拟信号的值与第一控制值之间的第一差的符号，以确定符号翻转，其中第一控制值为 可变值，并且基于所确定的第一差异的符号来生成可调谐频率的数字信号，其中生成可调谐频率的数字信号，使得信号电平的开关的子集与相应的符号翻转 的确定的第一个差异的迹象。

公开(公告)号：US09312863B2

公开(公告)日：2016-04-12

申请号：US14322758

申请日：2014-07-02

申请人： Broadcom Corporation

发明人： Tim Sippel

IPC分类号： H03L7/08 ,  H03K3/03 ,  H03K3/037 ,  H03K19/01 ,  G06F12/14 ,  G06F21/44 ,  H03K5/13 ,  H03L7/097 ,  H03L7/099 ,  G06F1/32 ,  G06F1/26 ,  H03K5/00

CPC分类号： H03L7/0802 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3228 ,  G06F12/14 ,  G06F21/44 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/037 ,  H03K3/0375 ,  H03K5/133 ,  H03K19/01 ,  H03K2005/00019 ,  H03K2005/00026 ,  H03K2005/00058 ,  H03L7/097 ,  H03L7/0997 ,  H01L2924/00

摘要： Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.

摘要翻译： 实施例提供了用于基于IC电源电压来动态地调节集成电路（IC）的时钟频率的系统和方法。 通过这样做，时钟频率不再受最坏情况电压电平的约束，并且可以支持更高的有效时钟频率，从而提高了IC性能。 实施例包括波时钟系统，其使用被配置为基本上匹配IC的相应逻辑路径的延迟的多个延迟链。 随着逻辑路径的延迟随电源电压和温度变化而变化，与逻辑路径相匹配的延迟链经历基本相似的改变，并用于调节IC的时钟频率。