公开(公告)号：US08357570B2

公开(公告)日：2013-01-22

申请号：US13052114

申请日：2011-03-21

Applicant: Yu-Cheng Chen

Inventor： Yu-Cheng Chen

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L27/1288 ,  H01L27/1214

Abstract: A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode.

Abstract translation: 一种制造像素结构的方法包括提供具有像素区域的衬底。 在衬底上形成第一金属层，栅极绝缘体和半导体层，并通过使用第一半色调掩模或灰色蒙版掩模进行图案化以形成晶体管图案，较低的电容图案和较低的电路图案。 接下来，依次形成覆盖三个图案的电介质层和电极层，并对其进行图案化以暴露下部电路图案的一部分，下部电容图案的一部分和晶体管图案的源极/漏极区域。 通过使用第二半色调掩模或灰度蒙版来形成在电极层和电极层上形成的第二金属层，以形成上部电路图案，源极/漏极图案和上部电容图案。 电极层的一部分构成像素电极。

公开(公告)号：US20120223312A1

公开(公告)日：2012-09-06

申请号：US13471713

申请日：2012-05-15

Applicant: Yu-Cheng Chen

Inventor： Yu-Cheng Chen

IPC: H01L29/786

CPC classification number: H01L27/1248 ,  G02F1/136213 ,  H01L27/1255

Abstract: A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.

Abstract translation: 提供了一种显示装置的半导体结构及其制造方法。 半导体结构形成在其上具有TFT区域和像素电容器区域的基板上。 在基板的TFT区域上形成包括栅电极，源电极，漏电极，沟道层和栅极绝缘层的TFT。 像素电容器形成在像素电容器区域上，其中像素电容器包括形成在底部电介质层上的底部电极，形成在底部电极上的层间电介质层，形成在层间电介质层上的顶部电极， 通过所述层间绝缘层和电连接到所述顶部和底部电极，形成在所述顶部电极上的电容器电介质层，形成在所述电容器电介质层上并电连接到所述漏极的透明电极。

公开(公告)号：US08202770B2

公开(公告)日：2012-06-19

申请号：US12815513

申请日：2010-06-15

Applicant: Yu-Cheng Chen

Inventor： Yu-Cheng Chen

IPC: H01L21/00

CPC classification number: H01L27/1248 ,  G02F1/136213 ,  H01L27/1255

Abstract: A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.

Abstract translation: 提供了一种显示装置的半导体结构及其制造方法。 半导体结构形成在其上具有TFT区域和像素电容器区域的基板上。 在基板的TFT区域上形成包括栅电极，源电极，漏电极，沟道层和栅极绝缘层的TFT。 像素电容器形成在像素电容器区域上，其中像素电容器包括形成在底部电介质层上的底部电极，形成在底部电极上的层间电介质层，形成在层间电介质层上的顶部电极， 通过所述层间绝缘层和电连接到所述顶部和底部电极，形成在所述顶部电极上的电容器电介质层，形成在所述电容器电介质层上并电连接到所述漏极的透明电极。

公开(公告)号：US08198149B2

公开(公告)日：2012-06-12

申请号：US13349586

申请日：2012-01-13

Applicant: Ming-Wei Sun ,  Chen-Yueh Li ,  Yu-Cheng Chen ,  Chia-Tien Peng

Inventor： Ming-Wei Sun ,  Chen-Yueh Li ,  Yu-Cheng Chen ,  Chia-Tien Peng

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L27/14692 ,  H01L27/1214 ,  H01L27/1288 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/14645

Abstract: A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.

Abstract translation: 提供一种用于制造有源器件阵列衬底的方法。 第一图案化半导体层，栅极绝缘体，第一图案化导电层和第一介电层依次形成在衬底上。 暴露第一图案化半导体层的第一接触孔形成在第一介电层和栅极绝缘体中。 第一图案化导电层和设置在其上的第二图案化半导体层同时形成在第一介电层上。 第二导电层包括接触导体和底部电极。 第二图案化半导体层包括有源层。 具有第二接触孔的第二电介质层形成在第一电介质层上，其中一部分第二接触孔露出有源层。 通过第二接触孔的一部分电连接到有源层的第三图案化导电层形成在第二介电层上。

公开(公告)号：US20120057090A1

公开(公告)日：2012-03-08

申请号：US13030133

申请日：2011-02-18

Applicant: Yu-Cheng Chen ,  Yi-Hui Li ,  Chih-Hung Lin ,  Maw-Song Chen

Inventor： Yu-Cheng Chen ,  Yi-Hui Li ,  Chih-Hung Lin ,  Maw-Song Chen

IPC: G02F1/1343

CPC classification number: G02F1/136213 ,  G02F1/133707

Abstract: An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain.

Abstract translation: 提供有源器件，像素结构和显示面板。 像素结构包括扫描线，数据线，有源器件，栅极绝缘层，像素电极，电容器电极和电容器电介质层。 有源器件包括栅极，沟道，源极和漏极。 栅极电连接到扫描线。 源电连接到数据线。 栅极绝缘层设置在栅极和沟道之间。 像素电极电连接到漏极。 电容电极位于栅极绝缘层上。 电容器电介质层位于电容器电极和漏极之间。

公开(公告)号：US20120023210A1

公开(公告)日：2012-01-26

申请号：US12960103

申请日：2010-12-03

Applicant: Te-Hsien LAI ,  Yu-Cheng Chen ,  Ching-Fu Kung

Inventor： Te-Hsien LAI ,  Yu-Cheng Chen ,  Ching-Fu Kung

IPC: G06F15/173

CPC classification number: H04L29/08072 ,  G06F9/46 ,  G06F11/3055 ,  G06F15/17325 ,  H04L69/329

Abstract: An operation method for a server system includes: (A) under control of a hardware abstraction layer (HAL), a plurality of node management units sharing a hardware resource; (B) if one of the node management units needs to use the hardware resource, the node management unit sending an instruction or a data to the HAL and accordingly the HAL using the hardware resource in represent of the node management unit; and (C) if an external instruction is received, the HAL identifying which transmission port of the hardware resource receives the external instruction, so to send the external instruction to a corresponding node management unit, and after the external instruction is executed, the corresponding node management unit sending back an information to the HAL so that the HAL sends back the information to an external system administrator.

Abstract translation: 一种服务器系统的操作方法，包括：（A）在硬件抽象层（HAL）的控制下，共享硬件资源的多个节点管理单元; （B）如果其中一个节点管理单元需要使用硬件资源，则节点管理单元使用代表节点管理单元的硬件资源向HAL发送指令或数据，并相应地发送HAL; 和（C）如果接收到外部指令，则HAL识别硬件资源的哪个传输端口接收外部指令，以便将外部指令发送到对应的节点管理单元，并且在执行外部指令之后，对应的节点 管理单元向HAL发回信息，以便HAL将信息发送回外部系统管理员。

公开(公告)号：US20110273654A1

公开(公告)日：2011-11-10

申请号：US12814503

申请日：2010-06-14

Applicant: Tsan-Chun Wang ,  Yu-Cheng Chen

Inventor： Tsan-Chun Wang ,  Yu-Cheng Chen

IPC: G02F1/1343

CPC classification number: G02F1/1368 ,  G02F1/13624

Abstract: An active device array substrate includes a substrate, scan lines disposed on the substrate, data lines intersected with the scan lines, scan signal transmission lines, and pixel units. The scan signal transmission lines are intersected with the scan lines. Each scan signal transmission line connects one scan line through a node. The pixel unit electrically connects the corresponding data line and the corresponding scan line and includes an active device and a pixel electrode. The active device has a gate, a source, and a drain. The pixel electrode electrically connects the drain. In the pixel units not adjacent to the nodes, a gate-to-drain capacitance of each active device is Cgd1. In the pixel units adjacent to the nodes, the gate-to-drain capacitances of some active devices are Cgd2, the gate-to-drain capacitances of the other active devices are Cgd1, and Cgd1≠Cgd2.

Abstract translation: 有源器件阵列衬底包括衬底，设置在衬底上的扫描线，与扫描线相交的数据线，扫描信号传输线和像素单元。 扫描信号传输线与扫描线相交。 每条扫描信号传输线通过一个节点连接一条扫描线。 像素单元电连接对应的数据线和相应的扫描线，并且包括有源器件和像素电极。 有源器件具有栅极，源极和漏极。 像素电极电连接漏极。 在与节点不相邻的像素单元中，每个有源器件的栅极 - 漏极电容为Cgd1。 在与节点相邻的像素单元中，一些有源器件的栅极至漏极电容为Cgd2，其他有源器件的栅极至漏极电容为Cgd1，Cgd1≠Cgd2。

公开(公告)号：US07982807B2

公开(公告)日：2011-07-19

申请号：US11736586

申请日：2007-04-18

Applicant: Yu-Cheng Chen

Inventor： Yu-Cheng Chen

IPC: H04N9/64

CPC classification number: H04N5/2351 ,  H04N5/243

Abstract: A method for processing an image includes inputting an image, generating a first mean luminance value and a second mean luminance value according to a plurality of pixels within a first luminance interval and a second luminance interval of the image, generating a first luminance threshold according to the first mean luminance value, setting a compensation parameter, generating a first compensation luminance value according to the first mean luminance value and the compensation parameter, generating a second compensation luminance value according to the first luminance threshold, the first mean luminance value, the second mean luminance value, and the compensation parameter, and adjusting luminance values of pixels within the a smaller compensation luminance value and a greater compensation luminance value according to the smaller compensation value and a comparison between the first compensation luminance value and the second compensation luminance value.

Abstract translation: 一种处理图像的方法包括输入图像，根据图像的第一亮度区间和第二亮度区间内的多个像素生成第一平均亮度值和第二平均亮度值，根据图像生成第一亮度阈值 第一平均亮度值，设定补偿参数，根据第一平均亮度值和补偿参数产生第一补偿亮度值，根据第一亮度阈值，第一平均亮度值，第二平均亮度值产生第二补偿亮度值 平均亮度值和补偿参数，以及根据较小的补偿值以及第一补偿亮度值和第二补偿亮度值之间的比较，调整较小补偿亮度值内的像素的亮度值和更大的补偿亮度值。

公开(公告)号：US07863616B2

公开(公告)日：2011-01-04

申请号：US12333313

申请日：2008-12-12

Applicant: Yu-Cheng Chen

Inventor： Yu-Cheng Chen

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L31/062

CPC classification number: H01L27/1248 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/42384

Abstract: A substrate having a gate electrode layer, a gate insulating layer, and a silicon layer thereon is provided. These layers are patterned into a gate area, a gate line and a gate line wiring area. A passivation layer is formed on the entire substrate and patterned to form two contact holes in the passivation layer on the silicon layer at the gate area, and partions of the passivation layer at the gate line and at the gate line wiring areas are removed. An ion implanting layer and a metal layer are formed on the substrate and patterned to form a source region, a drain region, a data line, a data line wiring area and a second layer of the gate line wiring area. A pixel electrode is formed on the passivation layer and electrically coupled to the drain region. Therefore, the TFT array can be fabricated by only four masks.

Abstract translation: 提供了具有栅极电极层，栅极绝缘层和硅层的衬底。 这些层被图案化成栅极区域，栅极线和栅极线路布线区域。 在整个基板上形成钝化层并图案化以在栅极区域的硅层上的钝化层中形成两个接触孔，并且去除栅极线处和栅极线路布线区域处的钝化层的一部分。 在衬底上形成离子注入层和金属层，并将其图案化以形成栅极线布线区域的源极区域，漏极区域，数据线，数据线布线区域和第二层。 像素电极形成在钝化层上并电耦合到漏区。 因此，TFT阵列可以仅由四个掩模制造。

公开(公告)号：US20100221859A1

公开(公告)日：2010-09-02

申请号：US12781135

申请日：2010-05-17

Applicant: Yu-Cheng Chen

Inventor： Yu-Cheng Chen

IPC: H01L21/336

CPC classification number: H01L27/124 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2201/40

Abstract: A semiconductor structure and a method for manufacturing the same are provided. Compared to conventional structures of thin film transistors, the structure of the present invention uses a patterned first metal layer as a data line, and a patterned second metal layer as a gate line. In a thin film transistor, a gate is also located in the patterned first metal layer, and is electrically connected to the gate line located in the patterned second metal layer through a contact hole. A source and a drain of the thin film transistor are electrically connected to the data line through a contact hole. The structure of the present invention increases a storage capacitance and an aperture ratio.

Abstract translation: 提供半导体结构及其制造方法。 与传统的薄膜晶体管结构相比，本发明的结构使用图案化的第一金属层作为数据线，并且图案化的第二金属层用作栅极线。 在薄膜晶体管中，栅极也位于图案化的第一金属层中，并且通过接触孔电连接到位于图案化的第二金属层中的栅极线。 薄膜晶体管的源极和漏极通过接触孔电连接到数据线。 本发明的结构增加了存储电容和开口率。