公开(公告)号：US5293490A

公开(公告)日：1994-03-08

申请号：US54821

申请日：1993-04-30

申请人： Ichiro Sasaki ,  Kouzi Nakayama

发明人： Ichiro Sasaki ,  Kouzi Nakayama

IPC分类号： G06F5/10 ,  G06K15/00 ,  G06F13/28

CPC分类号： G06F5/10 ,  G06K15/00 ,  G06F2205/108 ,  G06K2215/0022 ,  G06K2215/0077

摘要： A data buffering device having a data buffer permitting data storage in a first storage area A while the area A is advanced over a predetermined number of storage areas of the buffer in a predetermined sequence and permitting data reading from a second storage area B while the area B is advanced in the same sequence; a first device judging whether or not it is permissible to carry out at least one of a simple data storage and a simple data reading; a second device executing, if the judgement of the first device is negative, a return judgement whether or not it is necessary to return a corresponding one, or each, of the areas A and B to a leading storage area of the buffer, and a possibility judgement whether or not the buffer has at least a predetermined number of storage area or areas permitting a corresponding one, or each, of a data storage and a data reading, if the possibility judgement is affirmative the second device placing the first device in a condition in which the first device provides an affirmative judgement, and carrying out the corresponding one or each of the data storage and reading; and a third device carrying out, if the judgement of the first device is affirmative, the at least one of the simple data storage and reading, without the return and possibility judgements of the second device.

摘要翻译： 一种数据缓冲装置，具有允许在第一存储区域A中数据存储的数据缓冲器，同时区域A以预定顺序超过缓冲器的预定数量的存储区域，并允许从第二存储区域B读取数据，同时区域 B以相同的顺序进行; 判断是否允许执行简单数据存储和简单数据读取中的至少一个的第一设备; 第二装置，如果第一装置的判断为否定，则返回判断是否需要将区域A和B中的相应的一个或每个返回到缓冲器的前导存储区域，以及 如果可能性判断是肯定的，则缓冲器是否具有允许数据存储和数据读取中的相应的一个或每个的至少预定数量的存储区域的可能性判断，第二设备将第一设备放置在 第一装置提供肯定判断的条件，并执行对应的一个或每个数据存储和读取; 以及第三设备，如果所述第一设备的判断是肯定的，则执行所述简单数据存储和读取中的所述至少一个，而没有所述第二设备的返回和可能性判断。

公开(公告)号：US5016221A

公开(公告)日：1991-05-14

申请号：US444741

申请日：1989-12-01

申请人： James R. Hamstra

发明人： James R. Hamstra

IPC分类号： G06F5/10 ,  G06F13/12 ,  G11C7/00 ,  H04L13/08

CPC分类号： G06F5/10 ,  G06F13/128 ,  G06F2205/108

摘要： A first-in, first-out (FIFO) memory configuration comprising a fully addressable memory (e.g. random access memory), a write pointer, a read pointer, and a third, "commit" pointer serving as a boundary between first and second subsets of data stored within the FIFO. During data reception, a comparator circuit compares a predetermined subset of imcoming data with a predefined reference data set for determining whether the incoming data should be stored or aborted. This determination establishes the appropriate memory address value for positioning the commit pointer. The first subset of data behind the commit pointer may selectively be stored, while the second subset of data ahead of the commit pointer may selectively be aborted. During data transmission, a status register monitors the readiness of the data medium onto which the data is to be transmitted. If and/or when the data medium is ready to accept data, the commit pointer may be selectively positioned to demarcate data committed for transmission.

公开(公告)号：US4507760A

公开(公告)日：1985-03-26

申请号：US407877

申请日：1982-08-13

申请人： Alexander G. Fraser

发明人： Alexander G. Fraser

IPC分类号： H04L13/08 ,  G06F5/06 ,  G06F5/10 ,  G06F5/12 ,  G11C7/00

CPC分类号： G06F5/10 ,  G06F2205/108

摘要： A first-in, first-out queue has a random access memory (RAM) for storing a plurality of information words, seriatim. A controller is used to insure that only after a complete message, comprising the information words, has been received will a word of that message be read out. Three pointers are used to effect this result. A read pointer addresses the location in the RAM from where a word may be read. A write pointer addresses the location in the RAM where a word may be entered. A third pointer addresses the location in the RAM where the last word of a complete message is stored.

摘要翻译： 先入先出队列具有用于存储多个信息字的随机存取存储器（RAM）。 控制器用于确保只有在已经接收到包括信息字的完整消息之后，才能读出该消息的单词。 使用三个指针来实现此结果。 读取指针寻址RAM中可能读取单词的位置。 一个写指针指向RAM中可能输入单词的位置。 第三个指针指向RAM中存储完整消息的最后一个字的位置。

公开(公告)号：US20110314190A1

公开(公告)日：2011-12-22

申请号：US13222757

申请日：2011-08-31

申请人： Tetsuya TANAKA

发明人： Tetsuya TANAKA

IPC分类号： G06F3/00

CPC分类号： G06F5/10 ,  G06F5/065 ,  G06F2205/108

摘要： As a FIFO buffer system, a rewind function is realized without reducing a data transfer rate. Input data is written in a write FIFO buffer, and is packetized by a packetizing FIFO buffer to be written in a buffer memory area formed in a save memory. A multiplexer selects, in a first mode, an output of the write FIFO buffer, and in a second mode, packet data read from the buffer memory area. The multiplexer continuously selects the first mode until the read FIFO buffer becomes full.

摘要翻译： 作为FIFO缓冲器系统，在不降低数据传输速率的情况下实现倒带功能。 输入数据写入写入FIFO缓冲器，并由打包FIFO缓冲器分组，以写入保存存储器中形成的缓冲存储器区域。 复用器在第一模式中选择写FIFO缓冲器的输出，并且在第二模式中，从缓冲存储器区域读取分组数据。 多路复用器连续选择第一个模式，直到读FIFO缓冲区变满。

公开(公告)号：US20100312985A1

公开(公告)日：2010-12-09

申请号：US12481397

申请日：2009-06-09

申请人： Steven D. Rostedt

发明人： Steven D. Rostedt

IPC分类号： G06F12/06

CPC分类号： G06F9/52 ,  G06F5/10 ,  G06F11/3636 ,  G06F2205/064 ,  G06F2205/108

摘要： In one embodiment, a mechanism for a lockless ring buffer in overwrite mode is disclosed. In one embodiment, a method for implementing a lockless ring buffer in overwrite mode includes aligning memory addresses for each page of a ring buffer to form maskable bits in the address to be used as a state flag for the page and utilizing at least a two least significant bits of each of the addresses to represent the state flag associated with the page represented by the address, wherein the state flag indicates one of three states including a header state, an update state, and a normal state. The method further includes combining a movement of a head page pointer to a head page of the ring buffer with a swapping of the head page and a reader page, the combining comprising updating the state flag of the head page pointer to the normal state and updating the state flag of a pointer to the page after the head page to the header state, and moving the head page and a tail page of the ring buffer, the moving comprising updating the state flags of one or more pointers in the ring buffer associated with the head page and the tail page.

摘要翻译： 在一个实施例中，公开了一种用于重写模式下的无锁环缓冲器的机构。 在一个实施例中，一种用于在重写模式中实现无锁环缓冲器的方法包括：对于环形缓冲器的每个页面的存储器地址进行对齐，以形成地址中的可屏蔽位，以用作页面的状态标志，并且利用至少两个最小值 每个地址的有效位表示与由地址表示的页相关联的状态标志，其中状态标志指示包括报头状态，更新状态和正常状态的三种状态之一。 该方法还包括将首页指针与环形缓冲器的头部页面的移动与头部页面和读取器页面的交换相结合，该组合包括将头部页面指针的状态标志更新为正常状态并更新 在首页到头部状态之后的指向页面的指针的状态标志，以及移动环形缓冲器的头部页面和尾页，移动包括更新与相关联的环形缓冲器中的一个或多个指针的状态标志 首页和尾页。

公开(公告)号：US07639707B2

公开(公告)日：2009-12-29

申请号：US11237481

申请日：2005-09-27

申请人： Chris Haywood

发明人： Chris Haywood

IPC分类号： H04L12/54

CPC分类号： G06F12/0875 ,  G06F5/10 ,  G06F2205/108 ,  H04L49/90 ,  H04L49/9042 ,  H04L49/9073

摘要： A variable size first in first out (FIFO) memory is disclosed. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.

摘要翻译： 公开了先进先出（FIFO）存储器中的可变大小。 可变大小FIFO存储器可以包括以非常高的数据速率工作的头和尾FIFO存储器以及片外缓冲存储器。 片外缓冲存储器可以是例如动态RAM类型。 当前端和后端FIFO存储器都满时，片外缓冲存储器可临时存储数据包。 每个存储器的数据块可以具有相同的尺寸以便有效地传输数据。 在导致存储器溢出的突发数据突发停止之后，头部和尾部FIFO存储器返回到其初始功能，其中头FIFO存储器直接接收高速数据并将其发送到各种开关元件，并且尾部FIFO存储器存储数据的临时溢出 头FIFO存储器。

公开(公告)号：US07353344B2

公开(公告)日：2008-04-01

申请号：US10972771

申请日：2004-10-26

申请人： Jun Tsuiki

发明人： Jun Tsuiki

IPC分类号： G06F13/00

CPC分类号： G06F5/10 ,  G06F2205/108

摘要： The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input. It provides a storage device capable of unloading data of arbitrary data length from data areas quickly. The storage device is equipped with a start position pointer which additionally stores the write position before the change each time a write position memorized by a write pointer is changed due to data input. When areas are freed, new read positions are determined based on saved write positions and the number of data items to be unloaded.

摘要翻译： 本发明涉及一种接收任意数据长度数据输入的存储装置，存储数据，并按输入顺序输出存储的数据。 它提供了能够快速从数据区域卸载任意数据长度的数据的存储设备。 存储装置配备有起始位置指示器，其在由写入指针存储的写入位置由于数据输入而改变时，另外存储改变之前的写入位置。 当区域被释放时，基于保存的写入位置和要卸载的数据项的数量来确定新的读取位置。

公开(公告)号：US20060072598A1

公开(公告)日：2006-04-06

申请号：US11237481

申请日：2005-09-27

申请人： Chris Haywood

发明人： Chris Haywood

IPC分类号： H04L12/56

CPC分类号： G06F12/0875 ,  G06F5/10 ,  G06F2205/108 ,  H04L49/90 ,  H04L49/9042 ,  H04L49/9073

摘要： A variable size first in first out (FIFO) memory is disclosed. The variable size FIFO memory may include head and tail FIFO memories operating at a very high data rate and an off chip buffer memory. The off chip buffer memory may be, for example, of a dynamic RAM type. The off chip buffer memory may temporarily store data packets when both head and tail FIFO memories are full. Data blocks of each of the memories may be the same size for efficient transfer of data. After a sudden data burst which causes memory overflow ceases, the head and tail FIFO memories return to their initial functions with the head FIFO memory directly receiving high speed data and transmitting it to various switching element and the tail FIFO memory storing temporary overflows of data from the head FIFO memory.

公开(公告)号：US06996640B1

公开(公告)日：2006-02-07

申请号：US10935013

申请日：2004-09-03

申请人： Timothy R. Hill ,  Thomas Trocine

发明人： Timothy R. Hill ,  Thomas Trocine

IPC分类号： G06F3/00

CPC分类号： G06F5/14 ,  G06F2205/063 ,  G06F2205/108

摘要： The present invention provides method, data transfer controller and system for asynchronously transferring data. The method allows to provide a buffer device. The method further allows to define in the buffer device a plurality of buffer segments. Respective ones of the buffer segments are filled with data from at least one data source device operating in a respective clock domain. Upon any respective buffer segment being filled up, the method allows to generate an indication of availability of the contents of the respective buffer segment to at least one data destination device operating in a respective clock domain. The clock domain of the at least one source device is distinct than the clock domain of the at least one destination device.

摘要翻译： 本发明提供用于异步传送数据的方法，数据传输控制器和系统。 该方法允许提供缓冲装置。 该方法还允许在缓冲器中定义多个缓冲区段。 相应的缓冲区块中的每一个都填充有来自在相应时钟域中操作的至少一个数据源设备的数据。 在任何相应的缓冲区段被填满之后，该方法允许生成对相应时钟域中操作的至少一个数据目的地设备的相应缓冲区段的内容的可用性的指示。 所述至少一个源设备的时钟域与所述至少一个目的地设备的时钟域不同。

公开(公告)号：US20060026368A1

公开(公告)日：2006-02-02

申请号：US10972771

申请日：2004-10-26

申请人： Jun Tsuiki

发明人： Jun Tsuiki

IPC分类号： G06F13/00

CPC分类号： G06F5/10 ,  G06F2205/108

摘要： The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input. It provides a storage device capable of unloading data of arbitrary data length from data areas quickly. The storage device is equipped with a start position pointer which additionally stores the write position before the change each time a write position memorized by a write pointer is changed due to data input. When areas are freed, new read positions are determined based on saved write positions and the number of data items to be unloaded.

摘要翻译： 本发明涉及一种接收任意数据长度数据输入的存储装置，存储数据，并按输入顺序输出存储的数据。 它提供了能够快速从数据区域卸载任意数据长度的数据的存储设备。 存储装置配备有起始位置指示器，其在由写入指针存储的写入位置由于数据输入而改变时，另外存储改变之前的写入位置。 当区域被释放时，基于保存的写入位置和要卸载的数据项的数量来确定新的读取位置。