公开(公告)号：US20100039078A1

公开(公告)日：2010-02-18

申请号：US12370614

申请日：2009-02-13

申请人： Masakatsu SUDA

发明人： Masakatsu SUDA

IPC分类号： G05F1/70

CPC分类号： H03K19/00346

摘要： Provided is a load fluctuation compensation circuit for compensating a power source voltage supplied to an operation circuit, the load fluctuation compensation circuit including: a periodic signal changing section that receives a power source voltage from a power source shared with the operation circuit, and outputs a changed signal resulting from changing a supplied periodic signal according to the power source voltage; a phase comparator that compares a phase of the periodic signal with a phase of the changed signal outputted from the periodic signal changing section; an initializing section that generates a bias voltage supplied to the periodic signal changing section and adjusts a phase difference between the periodic signal and the changed signal to a preset value, based on the comparison result of the phase comparator; a controller that holds the bias voltage outputted from the initializing section when the phase difference between the periodic signal and the changed signal has become the preset value; a power current consumption circuit that shares a power source with the operation circuit; and a fluctuation compensation section that controls an amount of a power current supplied to the power current consumption circuit, based on the comparison result outputted from the phase comparator while the bias voltage of the initializing section is kept on hold.

摘要翻译： 提供一种用于补偿提供给操作电路的电源电压的负载波动补偿电路，所述负载波动补偿电路包括：周期性信号变化部，其从与所述运算电路共用的电源接收电源电压，并输出 根据电源电压改变提供的周期信号而产生的改变的信号; 相位比较器，将周期信号的相位与从周期信号变化部输出的变化信号的相位进行比较; 初始化部，其基于所述相位比较器的比较结果，生成提供给所述周期信号变更部的偏置电压，并将所述周期信号与所述变化的信号之间的相位差调整为预设值; 控制器，当周期信号和改变信号之间的相位差成为预设值时，保持从初始化部分输出的偏置电压; 与所述运行电路共用电源的电力消耗电路; 以及波动补偿部，其基于从所述初始化部的所述偏置电压保持在所述相位比较器输出的比较结果来控制供给所述电力消耗电路的电力量的量。

公开(公告)号：US07656954B1

公开(公告)日：2010-02-02

申请号：US11292372

申请日：2005-11-30

申请人： Peter J. Lim

发明人： Peter J. Lim

IPC分类号： H04B14/04 ,  H04B3/00

CPC分类号： H03K19/00346 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1078 ,  H03K19/0002

摘要： Embodiments for single-ended tri-level encoding and/or decoding of data are disclosed.

摘要翻译： 公开了用于数据的单端三级编码和/或解码的实施例。

公开(公告)号：US07649430B2

公开(公告)日：2010-01-19

申请号：US11863278

申请日：2007-09-28

申请人： Hiroaki Takeuchi ,  Yoshiyuki Hata

发明人： Hiroaki Takeuchi ,  Yoshiyuki Hata

IPC分类号： H01P1/10 ,  H03H7/24 ,  H01P5/12

CPC分类号： H03K19/00346 ,  H04L25/0264 ,  H04L25/0272

摘要： Provided is a switching apparatus connecting a transmission line designated among transmission lines, between input and output terminals, and preventing a signal at the terminal from leaking to a control wiring, becoming a noise, and being superposed onto a signal at the other end. The switching apparatus includes: a plurality of input series switches switching the connection state between one end of the transmission lines and the input terminal according to a control signal; a plurality of output series switches switching the connection state between the other end of the transmission lines and the output terminal according to a control signal; a plurality of control wirings that supply a control signal to the input series switch and the output series switch; and a noise removal section that is provided between the input series switch and the output series switch and that reduces a noise propagated via a control wiring.

摘要翻译： 提供一种连接在传输线之间，输入和输出端之间指定的传输线，并且防止端子处的信号泄漏到控制布线，成为噪声并且叠加在另一端的信号上的开关装置。 开关装置包括：多个输入串联开关，根据控制信号切换传输线的一端与输入端之间的连接状态; 多个输出串联开关根据控制信号切换传输线的另一端与输出端之间的连接状态; 多个控制线，其向输入串联开关和输出串联开关提供控制信号; 以及设置在输入串联开关和输出串联开关之间的噪声去除部分，并且减少了经由控制布线传播的噪声。

公开(公告)号：US07595679B1

公开(公告)日：2009-09-29

申请号：US11402252

申请日：2006-04-12

申请人： Mikhail Popovich ,  Eby G. Friedman ,  Radu M. Secareanu ,  Olin L. Hartin

发明人： Mikhail Popovich ,  Eby G. Friedman ,  Radu M. Secareanu ,  Olin L. Hartin

IPC分类号： H03K17/16

CPC分类号： H01L23/552 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03K19/00346 ,  H01L2924/0001

摘要： A system-on-chip or other circuit has an on-chip noise-free ground which is added to divert ground noise from the sensitive nodes. An on-chip decoupling capacitor, tuned in resonance with the parasitic inductance of the interconnects, can be provided to add an additional low impedance ground path.

摘要翻译： 片上系统或其他电路具有片上无噪声接地，用于转移敏感节点的接地噪声。 可以提供与互连的寄生电感谐振的片上去耦电容器，以增加额外的低阻抗接地路径。

公开(公告)号：US20090167380A1

公开(公告)日：2009-07-02

申请号：US12003468

申请日：2007-12-26

申请人： Christos P. Sotiriou

发明人： Christos P. Sotiriou

IPC分类号： H03L7/00

CPC分类号： H03K19/00346 ,  G06F1/10 ,  G06F9/3869 ,  H04B15/02

摘要： A system includes first and second synchronous circuits and an asynchronous circuit configured to receive input from the first synchronous circuit and to send output to the second synchronous circuit. First and second variable clock generators are configured to drive the first and second synchronous circuit. A delay circuit is configured in a pathway from the first variable clock generator to the second variable clock generator, the delay circuit being configured to add a delay to the pathway based upon a processing time or an expected processing time of the asynchronous circuit. The delay circuit is further configured to induce additional uneven delay into the pathway. The additional uneven delay disperses local current absorption, thereby decreasing overall electro magnetic emissions of the system.

摘要翻译： 一种系统包括第一和第二同步电路和异步电路，其被配置为从第一同步电路接收输入并将输出发送到第二同步电路。 第一和第二可变时钟发生器被配置为驱动第一和第二同步电路。 延迟电路被配置在从第一可变时钟发生器到第二可变时钟发生器的路径中，延迟电路被配置为基于异步电路的处理时间或期望的处理时间来向该路径添加延迟。 延迟电路还被配置为引起到该通路的额外的不均匀延迟。 额外的不均匀延迟分散局部电流吸收，从而降低系统的整体电磁发射。

公开(公告)号：US20090153182A1

公开(公告)日：2009-06-18

申请号：US12335331

申请日：2008-12-15

申请人： Masanao YAMAOKA ,  Kenichi Osada

发明人： Masanao YAMAOKA ,  Kenichi Osada

IPC分类号： H03K19/00

CPC分类号： H03K19/00346

摘要： A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay circuit that delays the first data and generates second data, and a second flip flop that stores the second data. Furthermore, the speed performance measurement circuit includes a first comparator circuit that compares output of the first flip flop to output of the second flip flop, and a third flip flop that stores output data from the first comparator circuit in accordance with timing of the first clock signal. Data in a normal path is compared to data in a path delayed by a certain time to measure speed, and power voltage of a circuit is determined based on such comparison. Thus, change in speed with respect to power voltage in a critical path can be measured.

摘要翻译： 可以在第一逻辑电路和第二逻辑电路之间提供可执行速度性能测量的速度性能测量电路。 速度性能测量电路包括存储第一数据的第一触发器，延迟第一数据并产生第二数据的第一延迟电路和存储第二数据的第二触发器。 此外，速度性能测量电路包括第一比较器电路，其将第一触发器的输出与第二触发器的输出进行比较;以及第三触发器，其根据第一时钟的定时存储来自第一比较器电路的输出数据 信号。 将正常路径中的数据与延迟一定时间的路径中的数据进行比较以测量速度，并且基于这样的比较确定电路的功率电压。 因此，可以测量关键路径中的功率电压的速度变化。

公开(公告)号：US07541947B2

公开(公告)日：2009-06-02

申请号：US11802886

申请日：2007-05-25

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

IPC分类号： H03M7/00

CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

公开(公告)号：US07535280B2

公开(公告)日：2009-05-19

申请号：US10836800

申请日：2004-04-30

申请人： John W. Fattaruso ,  Benjamin J. Sheahan

发明人： John W. Fattaruso ,  Benjamin J. Sheahan

IPC分类号： H03L5/00

CPC分类号： H03K19/0136 ,  H03K17/04126 ,  H03K19/00346 ,  H03K19/00376 ,  H03K19/01812 ,  Y10T307/826

摘要： An apparatus for shifting a received signal at a first reference level to an output signal at a second reference level; the received signal including information-indicating signal values; includes: (a) an input locus for receiving the received signal; (b) an output locus for presenting the output signal; (c) a first signal-handling circuit coupled with the input locus and with the output locus and setting the second reference level at the output locus; and (d) a second signal-handling circuit coupled with the input locus and with the first signal-handling circuit; the first signal-handling circuit and the second signal-handling circuit cooperating to convey the information-indicating signal values from the input locus to the output locus.

摘要翻译： 一种用于将第一参考电平的接收信号移位到第二参考电平的输出信号的装置; 所述接收信号包括信息指示信号值; 包括：（a）用于接收接收信号的输入轨迹; （b）用于呈现输出信号的输出轨迹; （c）第一信号处理电路，与输入轨迹和输出轨迹耦合，并将第二参考电平设置在输出轨迹处; 和（d）与输入轨迹和第一信号处理电路耦合的第二信号处理电路; 第一信号处理电路和第二信号处理电路协作地将信息指示信号值从输入轨迹传送到输出轨迹。

公开(公告)号：US07514952B2

公开(公告)日：2009-04-07

申请号：US11172568

申请日：2005-06-29

申请人： Eng H Lee ,  Kok W Loo

发明人： Eng H Lee ,  Kok W Loo

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/173 ,  H03K19/094 ,  G06F7/38 ,  H01H37/76 ,  H01H85/00

CPC分类号： H03K19/00346

摘要： Methods and circuitry for reducing ground bounce and VCC sag effects in integrated circuit (“IC”) devices is provided. In particular, a via-programmable design for I/O circuitry in IC devices is provided. The via-programmable I/O circuitry is used to disconnect I/O pin driver circuitry from and create a substantially direct connection between unused I/O pins and the ground and/or VCC signals of an IC device to reduce ground bounce and VCC sag, respectively.

摘要翻译： 提供了减少集成电路（“IC”）器件中的接地反弹和VCC下垂效应的方法和电路。 特别地，提供了用于IC器件中的I / O电路的通孔可编程设计。 通孔可编程I / O电路用于断开I / O引脚驱动器电路，并在未使用的I / O引脚与IC器件的接地和/或VCC信号之间实现基本上直接的连接，以减少接地反弹和VCC下垂 ， 分别。

公开(公告)号：US07408482B2

公开(公告)日：2008-08-05

申请号：US11266581

申请日：2005-11-03

申请人： Min-sang Park ,  Jin-seok Kwak ,  Seong-jin Jang

发明人： Min-sang Park ,  Jin-seok Kwak ,  Seong-jin Jang

IPC分类号： H03M5/00

CPC分类号： H03K19/00346

摘要： Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

摘要翻译： 集成电路装置包括其中的数据反转电路，其被配置为与由数据反相电路预先产生的有序输出数据组并行地评估至少第一和第二有序输入数据组。 数据反转电路还被配置为当输入的第一和第二有序组数据的第一有序组合的数量与第一有序数组组的输入 数据和有序的输出数据组大于输入数据的第一个有序组的大小的一半，输入数据的第二个有序组与输入数据的第一个有序组的版本之间的位数差异为 分别大于二阶输入数据组的二分之一。