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    ERROR-CORRECTION DECODER EMPLOYING CHECK-NODE MESSAGE AVERAGING
    51.
    发明申请
    ERROR-CORRECTION DECODER EMPLOYING CHECK-NODE MESSAGE AVERAGING 有权
    错误修正解码器使用检查节点消息平均

    公开(公告)号：US20100042891A1

    公开(公告)日：2010-02-18

    申请号：US12475786

    申请日：2009-06-01

    申请人： Kiran Gunnam ,  Shaohua Yang ,  Changyou Xu

    发明人： Kiran Gunnam ,  Shaohua Yang ,  Changyou Xu

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/1111 ,  H03M13/09 ,  H03M13/1142 ,  H03M13/3707 ,  H03M13/3738 ,  H03M13/3753 ,  H03M13/451

    摘要： In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). Each CNU is selectively configurable to operate in (i) a first mode that updates check-node (i.e., R) messages without averaging and (ii) a second mode that that updates R messages using averaging. Initially, each CNU is configured in the first mode to generate non-averaged R messages, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged R messages. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) each CNU is configured to operate in the second mode to generate averaged R messages, and (iii) the decoder attempts to recover the correct codeword using the averaged R messages. Averaging the R messages may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets.

    摘要翻译： 在一个实施例中，LDPC解码器具有控制器和一个或多个校验节点单元（CNU）。 每个CNU可选择性地配置为在（i）不平均更新校验节点（即，R）消息的第一模式和（ii）使用平均来更新R消息的第二模式。 最初，每个CNU被配置为第一模式以产生非平均的R消息，并且解码器尝试使用非平均的R消息来恢复LDPC编码的码字。 如果解码器不能恢复正确的码字，则（i）控制器选择平均模式，（ii）每个CNU被配置为在第二模式下操作以产生平均的R消息，并且（iii）解码器尝试恢复 使用平均R消息的正确码字。 平均R消息可能会减慢导致解码器收敛的错误消息的传播。

    DECODER AND RECORDING/REPRODUCING DEVICE
    52.
    发明申请
    DECODER AND RECORDING/REPRODUCING DEVICE 审中-公开
    解码器和记录/再现设备

    公开(公告)号：US20090327832A1

    公开(公告)日：2009-12-31

    申请号：US12410176

    申请日：2009-03-24

    申请人： Kazuhito Ichihara

    发明人： Kazuhito Ichihara

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G11B20/1833 ,  G11B2020/1836 ,  G11B2020/185 ,  G11B2020/1853 ,  H03M13/09 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/1515 ,  H03M13/19 ,  H03M13/2906 ,  H03M13/3738 ,  H03M13/3746 ,  H03M13/3753 ,  H03M13/3905 ,  H03M13/4146 ,  H03M13/6343

    摘要： A decoder and recording/reproducing device for preventing an increase in power consumption, has a multi-step iterative decoder. The decoder includes an iterative decoder in which a decoder constituted by a channel decoder and an outer code decoder is installed in multiple steps; an iterative decoding control circuit which estimates an error symbol count after decoding using likelihood information obtained from the outer decoder, stops the interactive decoding, if the estimated error symbol count exceeds an error symbols count, and corrects the residual errors that can be corrected by ECC using the ECC decoder. Therefore if a multi-step iterative decoder is used, the number of times of iterative decoding can be decreased and low power consumption can be implemented.

    摘要翻译： 用于防止功耗增加的解码器和记录/再现装置具有多步迭代解码器。 解码器包括迭代解码器，其中由多个步骤安装由信道解码器和外码解码器构成的解码器; 如果估计的误差符号计数超过错误符号计数，则使用从外部解码器获得的似然信息来估计解码之后的误差符号计数的迭代解码控制电路停止交互式解码，并且校正可由ECC校正的残余错误 使用ECC解码器。 因此，如果使用多步迭代解码器，则可以减少迭代解码的次数并且可以实现低功耗。

    Stochastic decoding of LDPC codes
    53.
    发明申请
    Stochastic decoding of LDPC codes 有权
    LDPC码的随机解码

    公开(公告)号：US20080077839A1

    公开(公告)日：2008-03-27

    申请号：US11902410

    申请日：2007-09-21

    申请人： Warren Gross ,  Shie Mannor

    发明人： Warren Gross ,  Shie Mannor

    IPC分类号： G06F11/10

    CPC分类号： H03M13/1137 ,  H03M13/1105 ,  H03M13/1134 ,  H03M13/1191 ,  H03M13/1194 ,  H03M13/19 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3753 ,  H03M13/658

    摘要： The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital bits. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the LDPC code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information bits. If an equality node is in a hold state a chosen bit is provided from a corresponding edge memory which is updated by storing output bits from the equality node when the same is in a state other than a hold state.

    摘要翻译： 本发明涉及一种用于LDPC码随机解码的解码方法和系统。 一组编码样本的每个编码样本首先按照与编码样本集合的噪声电平成比例的缩放因子来缩放。 然后将每个经缩放的编码样本转换成相应的概率。 对于每个概率，相应的概率消息是通过将每个概率编码为数字比特序列而生成的。 然后将每个概率消息提供给用于随机解码的逻辑电路的相应节点。 逻辑电路表示LDPC码的奇偶校验矩阵的因子图。 使用逻辑电路，每个概率消息被处理以确定信息比特的估计序列。 如果等式节点处于保持状态，则从相应的边缘存储器提供所选择的位，当对应的边缘存储器处于除保持状态之外的状态时，通过存储来自等式节点的输出位来更新。

    Method and apparatus for iterative decoding
    54.
    发明申请
    Method and apparatus for iterative decoding 失效
    用于迭代解码的方法和装置

    公开(公告)号：US20020196165A1

    公开(公告)日：2002-12-26

    申请号：US10219858

    申请日：2002-08-15

    申请人： Broadcom Corporation

    发明人： Ba-Zhong Shen ,  Kelly B. Cameron ,  Steven T. Jaffe

    IPC分类号： H03M007/00

    CPC分类号： H03M13/2906 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/2975 ,  H03M13/3753

    摘要： Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration, or the signature developed from an iteration prior to the previous iteration, the decoding stops. The variance may also be tested and compared to a threshold as a criteria to stop the iterative decoding.

    摘要翻译： 用于确定迭代解码过程的停止点的方法和装置。 在一个实施例中，将迭代解码器的迭代的估计值提供给签名电路。 如果签名与从先前迭代开始的先前签名或从前一次迭代之前的迭代开发的签名没有不同，则解码停止。 也可以测量方差并将其与阈值进行比较，作为停止迭代解码的标准。

    Stopping criteria for iterative decoding
    55.
    发明申请
    Stopping criteria for iterative decoding 有权
    停止迭代解码标准

    公开(公告)号：US20020067294A1

    公开(公告)日：2002-06-06

    申请号：US09900222

    申请日：2001-07-06

    发明人： Ba-Zhong Shen ,  Kelly B. Cameron ,  Steven T. Jaffe

    IPC分类号： H03M009/00

    CPC分类号： H03M13/2906 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/2975 ,  H03M13/3753

    摘要： Method and apparatus for determining the stopping point of an iterative decoding process. In one embodiment the estimated values of an iteration of an iterative decoder are provided to a signature circuit. If the signature does not differ from the previous signature developed from a prior iteration, or the signature developed from an iteration prior to the previous iteration, the decoding stops. The variance may also be tested and compared to a threshold as a criteria to stop the iterative decoding.

    摘要翻译： 用于确定迭代解码过程的停止点的方法和装置。 在一个实施例中，将迭代解码器的迭代的估计值提供给签名电路。 如果签名与从先前迭代开始的先前签名或从前一次迭代之前的迭代开发的签名没有不同，则解码停止。 也可以测量方差并将其与阈值进行比较，作为停止迭代解码的标准。

    Error floor performance improvement of generalized product codes
    56.
    发明授权
    Error floor performance improvement of generalized product codes 有权

    公开(公告)号：US11770137B1

    公开(公告)日：2023-09-26

    申请号：US17481296

    申请日：2021-09-21

    申请人： Infinera Corporation

    发明人： Mehdi Torbatian ,  Han Henry Sun

    IPC分类号： H03M13/29 ,  H03M13/25 ,  H03M13/37 ,  H03M13/45

    CPC分类号： H03M13/2909 ,  H03M13/251 ,  H03M13/3753 ,  H03M13/45

    摘要： Systems and methods for improving the error floor performance in decoding generalized product codes (GPC) are described. The systems and methods can implement a two stage process to decode a GPC block code and break a stall error pattern for the decoding the block code. In the first stage, erroneuous bits in a codeword can be flagged. In the second stage, some of these bits and related bits in a codeword can be toggled to generate one or more test patterns. The test patterns can be decoded and one of them can be selected using a particular selection criteria to ultimately break the stall error pattern and improve the error floor performance.

    TURBO EQUALIZATION DEVICE AND TURBO EQUALIZATION METHOD
    60.
    发明申请
    TURBO EQUALIZATION DEVICE AND TURBO EQUALIZATION METHOD 审中-公开

    公开(公告)号：US20170279559A1

    公开(公告)日：2017-09-28

    申请号：US15453481

    申请日：2017-03-08

    申请人： Panasonic Corporation

    发明人： TAKENORI SAKAMOTO

    IPC分类号： H04L1/00 ,  H03M13/00 ,  H03M13/37 ,  H04L25/03 ,  H03M13/11

    CPC分类号： H04L1/0051 ,  H03M13/1111 ,  H03M13/2957 ,  H03M13/3753 ,  H03M13/6331 ,  H04L1/0058 ,  H04L25/03019 ,  H04L25/067 ,  H04L2025/03611

    摘要： A turbo equalization device includes equalization circuitry, which in operation, performs an equalization process M times on an input signal, M being an integer equal to or more than 1; counter circuitry, which in operation, counts an iteration number m that indicates a number of the performed equalization process, m being an integer equal to or more than 0 and equal to less than M; control circuitry, which in operation, determines an iteration number N of a decoding process for the m times equalization processed input signal according to the iteration number m of the equalization process, the decoding process using an error correcting code that uses a belief propagation algorithm, N being an integer equal to or more than 1; and decoding circuitry, which in operation, performs a decoding process N or less times on the m times equalization processed input signal.