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公开(公告)号：US11687470B2
公开(公告)日：2023-06-27
申请号：US17860270
申请日：2022-07-08
申请人： Dell Products L.P.
发明人： Eric Kuzmack , Pawan Kumar Singal , Balaji Rajagopalan , Ning Zhuang , Joseph LaSalle White , Sudhir Vittal Shetty , Babu Krishna Chandrasekhar , Zoheb Khan
CPC分类号： G06F13/107 , G06F13/122 , G06F13/126
摘要： An expander I/O module discovery/management system includes a secondary system chassis housing an expander I/O module coupled to a server device. The server device identifies the secondary system chassis and an expander I/O module port utilized by that server device, and then generates and transmits an expander I/O module reporting communication identifying the secondary system chassis and the expander I/O module port. A primary system chassis houses a switching I/O module coupled to the expander I/O module. The switching I/O module receives the expander I/O module reporting communication and determines that the secondary system chassis identified in the expander I/O module reporting communication is different than the primary system chassis. In response, the switching I/O module assigns a virtual slot to the expander I/O module, and assigns a virtual port associated with the virtual slot to the expander I/O module port identified in the expander I/O module reporting communication.
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公开(公告)号：US20230185352A1
公开(公告)日：2023-06-15
申请号：US17551875
申请日：2021-12-15
IPC分类号： G06F1/3234 , G06F7/544 , G06N3/02 , G06F13/10
CPC分类号： G06F1/3234 , G06F7/5443 , G06N3/02 , G06F13/102
摘要： Methods, systems and computer program products are provided for improving performance (e.g., reducing power consumption) of a hardware accelerator (e.g., neural processor) comprising hybrid or analog multiply and accumulate (MAC) processing elements (PEs). Selective variation of the precision of an array of MAC PEs may reduce power consumption of a neural processor. Power may be conserved by dynamically controlling the precision of analog to digital (ADC) output bits for one or more MAC PEs. Dynamic control of ADC output bit precision may be based on precision information determined during training and/or post-training (e.g., quantization) of an artificial intelligence (AI) neural network (NN) model implemented by the neural processor. Precision information may include a range of dynamic precision for each of a plurality of nodes of a computation graph for the AI NN model.
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公开(公告)号：US20230169018A1
公开(公告)日：2023-06-01
申请号：US18071329
申请日：2022-11-29
发明人： Antonio PASCUCCI , Antonio DE DONNO
IPC分类号： G06F13/10
CPC分类号： G06F13/102
摘要： A method for creating a computer macro, the computer macro being executed on a computer, the computer including a processor, a display screen, a peripheral device, and a memory accessible by the processor, peripheral device, the method comprising: detecting, by a computer driver being at least partially resident in the memory, a computer program being at least partially resident in the memory to be executed in the computer; assigning, by the computer driver, at least one computer macro relating to the detected computer program to a key and/or button on the peripheral device; assigning, by the computer driver, a computer macro symbol relating to the assigned computer macro; storing, in the memory, the computer macro, the key and/or button on the peripheral device assigned to the computer macro and/or the assigned computer macro symbol; displaying, on the display screen via the computer driver, an on-screen-display, OSD, wherein the OSD is configured to display the assigned stored computer macro symbol and a reference relating to the stored key and/or button on the peripheral device to which the assigned stored computer macro has been assigned; and executing, by the processor, the stored computer macro assigned to the stored computer macro in the computer program when the stored key and/or button on the peripheral device is actuated.
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公开(公告)号：US11650930B2
公开(公告)日：2023-05-16
申请号：US17482676
申请日：2021-09-23
CPC分类号： G06F12/10 , G06F13/102 , G06F2212/657
摘要： A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.
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公开(公告)号：US11637783B2
公开(公告)日：2023-04-25
申请号：US17604236
申请日：2019-05-03
发明人： Tommy Arngren , Hans Hannu , Peter Ökvist , Stefan Wänstedt
IPC分类号： H04L47/283 , H04L65/65 , G06F13/10
摘要： A user terminal emulation server maintains a database identifying network addresses, UI capabilities, and communication protocols of I/O user devices. Communication sessions are established between a user terminal emulation application and a network entity and I/O user devices proximately located to a user and provide a combined I/O user interface. Delay profiles are determined between the application and the I/O user devices. A downlink flow from the network entity is split into a plurality of downlink flow components assigned to the I/O user devices. For each of the downlink flow components, the server formats the component for transmission to the assigned I/O user device, initiates transmission of the formatted downlink flow component to the assigned I/O user device, and controls timing for when the formatted downlink flow component is transmitted to the assigned I/O user device based on the delay profile associated with the assigned I/O user device.
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公开(公告)号：US20230111694A1
公开(公告)日：2023-04-13
申请号：US17448597
申请日：2021-09-23
申请人： Intel Corporation
IPC分类号： G06F1/26 , G06F1/3203 , G06F13/10
摘要： In an embodiment, a host system for selecting a power supply includes a processor, a bus interface to connect to a peripheral device, and a power controller. The power controller may be to: determine whether the processor has entered a reduced power mode; determine, via one or more bus messages, whether charging is to be performed for a battery of the peripheral device; and in response to a determination that the processor has entered the reduced power mode and that charging is not to be performed for the battery of the peripheral device, switch from a first power supply to a second power supply as an active power source of the host system. Other embodiments are described and claimed.
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公开(公告)号：US11625338B1
公开(公告)日：2023-04-11
申请号：US17452790
申请日：2021-10-29
发明人： Dwight D. Riley , Scott P. Faasse
摘要： A supervisory service of a node that includes a smart input/output (I/O) peripheral is extended into a cloud operator domain that is associated with the smart I/O peripheral. The supervisory service determines a state of a ready state indicator that is provided by the smart I/O peripheral. Based on the state, the supervisory service performs at least one of regulating an availability of an instance of an application operating environment of the node or determining whether the smart I/O peripheral is ready to be configured by the supervisory service.
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公开(公告)号：US11620190B2
公开(公告)日：2023-04-04
申请号：US17236757
申请日：2021-04-21
发明人： Georges Brun-Cottan , Jehuda Shemer , Arieh Don
摘要： Processing I/O operations may include: receiving, at a data storage system, an I/O operation from a host, wherein the I/O operation is directed to a logical address and includes an I/O tag used in connection with performing data reduction processing for first data stored at the logical address; and performing processing to back up a data set including the first data stored at the logical address. The processing may include: sending, from the data storage system to a backup application, the data set and hints regarding the first data set, wherein the hints include a first hint determined in accordance with the I/O tag from the host; performing, in accordance with the hints, data reduction processing of the data set to generate a second data set; and storing the second data set on one or more backup storage devices.
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公开(公告)号：US20230085904A1
公开(公告)日：2023-03-23
申请号：US18059771
申请日：2022-11-29
发明人： George Bein
摘要： Systems and methods for ground fault circuit interrupter trip detection and entire premises loss of power and restoration detection and notification of those events is disclosed. An example system may receive a smart plug identification. The system may authorize a smart plug. The system may link the smart plug to a smart plug application. The system may query the smart plug to obtain a power notification. The system may notify smart plug application of a power status.
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公开(公告)号：US11602685B2
公开(公告)日：2023-03-14
申请号：US17164942
申请日：2021-02-02
申请人： STEELSERIES ApS
发明人： Tino Soelberg
IPC分类号： A63F13/20 , A63F13/22 , A63F13/285 , G06F3/01 , G06F3/038 , A63F13/24 , A63F13/42 , G06F1/16 , G06F3/023 , G06F3/0354 , G06F3/039 , G06F9/445 , G06F13/10 , H01F7/02 , A63F13/60 , A63F13/63
摘要： A system that incorporates the subject disclosure may include, for example, a processor that performs operations including detecting a first depression range of a button that includes an electro-mechanical sensor for detecting the first depression range, comparing the first depression range to a first actuation threshold, and asserting a first actuation state when the first depression range is at or exceeds the first actuation threshold. Additional embodiments are disclosed.
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