公开(公告)号：US10531132B2

公开(公告)日：2020-01-07

申请号：US15856509

申请日：2017-12-28

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics, Inc.

Inventor： Udit Kumar ,  Bharat Jauhari ,  Chandandeep Singh Pabla

IPC: H04N21/438 ,  H04N21/234 ,  H04N21/44 ,  H04N5/44 ,  H04N21/433 ,  H04N21/434 ,  H04N21/482

Abstract: A channel stream is received and demultiplexed into a video packetized elementary stream (PES), audio packetized elementary stream (PES), and program clock reference (PCR). Indexing circuitry stores the video PES and the audio PES in a buffer, locates a presentation time stamp (PTS) in the video PES and stores that PTS in the buffer, locates a start of each group of pictures (GOP) in the video PES and stores those locations in the buffer, and locates a PTS in the audio PES and stores that PTS in the buffer. Control circuitry empties the buffer of an oldest GOP in the video PES if the PCR is greater than the PTS of a second oldest GOP stored in the buffer, and empties the buffer of each PES packet of the audio PES that has a PTS that is less than the PTS of the oldest GOP stored.

公开(公告)号：US10521921B2

公开(公告)日：2019-12-31

申请号：US15476100

申请日：2017-03-31

Applicant: STMicroelectronics (Research & Development) Limited ,  STMicroelectronics, Inc.

Inventor： Xiaoyong Yang ,  Neale Dutton

IPC: G01S17/89 ,  G06T7/55 ,  G06T7/73 ,  G06T7/521 ,  H04N5/235 ,  G01S17/02 ,  G01S7/48 ,  G01S7/497 ,  G06K9/00 ,  G07C9/00

Abstract: An apparatus includes time of flight single-photon avalanche diode (ToF SPAD) circuitry. The ToF SPAD circuitry generates indications of distance between the apparatus and an object within a field of view. A processor receives the indications of distance and controls at least one image sensor, such as a camera, to capture at least one image based on at least one indication of distance. The processor determines whether an image is a true representation of an expected object by comparing multiple indications of distance associated with the object to an expected object distance profile and comparing the image to at least one expected object image.

公开(公告)号：US10520552B2

公开(公告)日：2019-12-31

申请号：US15455321

申请日：2017-03-10

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics International N.V.

Inventor： K. R. Hariharasudhan ,  Frank J. Sigmund

IPC: G01R31/36 ,  G01R31/367 ,  G01R31/3842

Abstract: An electronic device includes a processor coupled to a battery and to determine whether the battery is being charged or discharged. If the battery being is being discharged, the processor operates to calculate an amount by which the battery has discharged since a preceding calculation of remaining capacity of the battery, compensate the amount by which the battery has discharged for a condition of the battery, and calculate a remaining capacity of the battery as a function of the amount by which the battery has discharged. If the battery is being charged, the processor operates to calculate an amount by which the battery has charged since a preceding calculation of remaining capacity of the battery, compensate the amount by which the battery has charged for a condition of the battery, and calculate the remaining capacity of the battery as a function of the amount by which the battery has charged.

公开(公告)号：US10480941B2

公开(公告)日：2019-11-19

申请号：US16284448

申请日：2019-02-25

Applicant: STMicroelectronics, Inc.

Inventor： Mahesh Chowdhary ,  Sankalp Dayal

IPC: G01C19/32 ,  G01C19/5776 ,  G01P15/18

Abstract: A sensor chip is mounted on a PCB and electrically connected to a SOC mounted on the PCB via at least one conductive trace. The sensor chip includes configuration registers storing and outputting configuration data, and a PLD receiving digital data. The PLD performs an extraction of features of the digital data in accordance with the configuration data, and the configuration data includes changeable parameters of the extraction. A classification unit processes the extracted features of the digital data so as to generate a context of an electronic device into which the sensor chip is incorporated relative to its surroundings, the processing being performed in using a processing technique operating in accordance with the configuration data. The configuration data also includes changeable parameters of the processing technique. The classification unit outputs the context to data registers for storage.

公开(公告)号：US10461019B2

公开(公告)日：2019-10-29

申请号：US16136709

申请日：2018-09-20

Applicant: STMicroelectronics, Inc.

Inventor： Aaron Cadag ,  Ian Harvey Arellano ,  Ela Mia Cadag

IPC: H01L21/44 ,  H01L23/495 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/544

Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.

公开(公告)号：US10446670B2

公开(公告)日：2019-10-15

申请号：US14953574

申请日：2015-11-30

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Bruce B. Doris ,  Hong He ,  Junli Wang ,  Nicolas J. Loubet

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L21/265 ,  H01L21/8238

Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

公开(公告)号：US10420140B2

公开(公告)日：2019-09-17

申请号：US15729017

申请日：2017-10-10

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov ,  Aidan Cully ,  David Lawrence ,  Michael J. Macaluso

IPC: H04W74/08 ,  H04L12/18 ,  H04L29/06 ,  H04B3/54 ,  H04L12/413 ,  H04L1/18 ,  H04L12/761 ,  H04L1/00

Abstract: Multicast transmissions are efficient but do not allow for individual acknowledgement that the data was received by each receiver. This is not acceptable for isochronous systems that require specific levels of QoS for each device. A multimedia communications protocol is provided that uses a novel multi-destination burst transmission protocol in multimedia isochronous systems. The transmitter establishes a bi-directional burst mode for multicasting data to multiple devices and receiving Reverse Start of Frame (RSOF) delimiters from each multicast-destination receiver in response to multiple SOF delimiters, thus providing protocol-efficient multi-destination acknowledgements.

公开(公告)号：US10354927B2

公开(公告)日：2019-07-16

申请号：US16027707

申请日：2018-07-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US10347569B2

公开(公告)日：2019-07-09

申请号：US15801022

申请日：2017-11-01

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/29

Abstract: Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead nearest the die pad. A support integral to the leadframe allows the support to be built to the proper height to support the cantilevered lead in each package and reduces or eliminates the upward, downward, and side to side deflections caused or allowed by supports built-in to the tooling of the manufacturing equipment. Also, by building the support into the leadframe, the leadframes may be pretaped prior to the die attach and wire bonding steps of the manufacturing process.

公开(公告)号：US10319816B2

公开(公告)日：2019-06-11

申请号：US16016021

申请日：2018-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  Nicolas Loubet ,  Junli Wang

IPC: H01L21/02 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/311 ,  H01L29/161 ,  H01L29/167

Abstract: A fin field effect transistor includes a Si fin including a central portion between end portions of the fin, and a SiGe channel region disposed on the central portion of the fin. The SiGe channel region includes a facet free SiGe region having Ge atoms diffused into the Si fin and includes a same shape as the Si fin outside the central portion.