公开(公告)号：US20040217839A1

公开(公告)日：2004-11-04

申请号：US10774055

申请日：2004-02-06

Applicant: STMICROELECTRONICS SA

Inventor： Bart Van Haaren ,  Cecile Clement ,  Daniel Gloria

IPC: H01F005/00

CPC classification number: H01L28/10 ,  H01F21/12 ,  H01F2021/125 ,  H01L27/08 ,  Y10T29/4902 ,  Y10T29/49071

Abstract: An integrated inductor comprises a first substantially plane conducting track made on the surface of a substrate and having a shape which defines a predetermined number N of concentric turns. A first pair of access points corresponds to the two respective ends of the said first conducting track. In addition, at least a second pair of access points different from the access points of the first pair, are placed at two respective regions of the first conducting track.

公开(公告)号：US20040210821A1

公开(公告)日：2004-10-21

申请号：US10799371

申请日：2004-03-12

Applicant: STMicroelectronics SA

Inventor： Bernard Kasser

IPC: G06K007/00

CPC classification number: H04L63/0428 ,  G06F21/10 ,  G06F2221/0797 ,  G06F2221/2153 ,  H04L63/062 ,  H04L63/0853

Abstract: The secure circulation of digital documents to be reproduced includes providing each user with a smart card containing identification information associated therewith, and identifying from a server connected to a digital data transmission network the smart card connected thereto. Information identifying a document to be played back is transmitted to the server from a terminal connected to the smart card. In response, a decryption key specific to the document to be reproduced is transmitted to the smart card for storing therein. The document to be played back is decrypted using an adapted reader connected to the smart card, and includes the stored decryption key for document playback with the reader. Information identifying the readers is inserted into the smart card, and fraudulent use of the smart card is determined according to the reader identification information stored in the smart card.

Abstract translation: 要再现的数字文档的安全流通包括向每个用户提供包含与其相关联的识别信息的智能卡，以及从连接到数字数据传输网络的服务器识别连接到其上的智能卡。 识别待播放文件的信息从连接到智能卡的终端发送到服务器。 作为响应，将要被再现的文档特定的解密密钥发送到智能卡以用于存储。 使用连接到智能卡的适配读取器对要播放的文档进行解密，并且包括用于与读取器进行文档回放的所存储的解密密钥。 将识别读取器的信息插入到智能卡中，并且根据存储在智能卡中的读取器识别信息确定智能卡的欺诈性使用。

公开(公告)号：US20040149808A1

公开(公告)日：2004-08-05

申请号：US10729827

申请日：2003-12-05

Applicant: STMicroelectronics SA

Inventor： Guillaume Bouche ,  Pascal Ancey ,  Benoit Froment

IPC: B23K031/02

CPC classification number: B81C1/00333 ,  H03H9/105 ,  H03H9/175

Abstract: A method for attaching a first element to a second element is provided. The first element has a surface portion covered with a layer of silicon, and the second element has a surface portion covered with a layer of nickel. The method includes applying pressure so that the surface portions of the first and second elements are in contact with one another. A roughness between the surface portions is less than about 1 nullm, and the first and second elements are heated within a range of about 250null C. to 400null C.

Abstract translation: 提供了将第一元件附接到第二元件的方法。 第一元件具有覆盖有硅层的表面部分，并且第二元件具有覆盖有镍层的表面部分。 该方法包括施加压力使得第一和第二元件的表面部分彼此接触。 表面部分之间的粗糙度小于约1um，第一和第二元件在约250℃至400℃的范围内被加热。

公开(公告)号：US20040115891A1

公开(公告)日：2004-06-17

申请号：US10689528

申请日：2003-10-20

Applicant: STMicroelectronics SA

Inventor： Yvon Gris

IPC: H01L021/336

CPC classification number: H01L28/20 ,  H01L27/0802

Abstract: A process for selectively doping predetermined resistive elements on an electronic chip is provided. The resistive elements are arranged in a pattern, and there are three phases in the process. The first phase electrically charges selected elements of the pattern. The second phase adds doping atoms to the charged elements as a function of their state of charge. The third phase anneals the electronic chip to cause penetration of the doping agents and to activate them.

Abstract translation: 提供了用于在电子芯片上选择性地掺杂预定电阻元件的工艺。 电阻元件以图案布置，并且在该过程中存在三个阶段。 第一阶段对所选择的图案元素进行电荷充电。 第二阶段根据其充电状态将掺杂原子添加到带电元件。 第三阶段使电子芯片退火以引起掺杂剂的渗透并激活它们。

公开(公告)号：US20040073762A1

公开(公告)日：2004-04-15

申请号：US10645321

申请日：2003-08-21

Applicant: STMicroelectronics SA

Inventor： Franck Roche ,  Didier Cavalli

IPC: G06F012/00

CPC classification number: G06F13/4022

Abstract: A microprocessor is connected to a first memory space through a first bus and to a second memory space through a second bus. The microprocessor includes a processing unit that includes a program bus and a data bus, and an interface unit connected, on one side, to the program bus and to the data bus and, on the other side, to the first and second buses. The interface includes a switching circuit for connecting the program bus and the data bus, respectively, to either the first bus or the second bus, in accordance with respective requests for accessing the program and data sent by the processing unit.

Abstract translation: 微处理器通过第一总线连接到第一存储器空间，并通过第二总线连接到第二存储器空间。 微处理器包括一个处理单元，它包括一个程序总线和一个数据总线，一个接口单元一方面连接到程序总线和数据总线，另一侧连接到第一和第二总线。 接口包括根据访问程序和由处理单元发送的数据的相应请求，将程序总线和数据总线分别连接到第一总线或第二总线的切换电路。

公开(公告)号：US20040054514A1

公开(公告)日：2004-03-18

申请号：US10447776

申请日：2003-05-29

Applicant: STMicroelectronics SA

Inventor： Philippe Flatresse ,  Mario Casu

IPC: G06F017/50 ,  H03K019/20

CPC classification number: G06F17/5022 ,  G06F17/5036

Abstract: A method for characterizing a CMOS logic cell of the partially depleted silicon-on-insulator type (PD-SOI) may include modeling the logic cell and determining internal potentials of transistors of the cell in a dynamic equilibrium state based upon a functional simulation of the modeled cell. This may be done using a binary stimulation signal having an initial logic value. The dynamic equilibrium state may be based upon a cancellation, to within a precision error, of the sum of the squares of variations in the quantities of charge in floating substrates of the transistors taken over a period of two successive transitions of the stimulation signal.

Abstract translation: 用于表征部分耗尽的绝缘体上硅类型（PD-SOI）的CMOS逻辑单元的方法可以包括对动态平衡状态下的逻辑单元建模并确定单元的晶体管的内部电位，该功能模拟基于 建模细胞。 这可以使用具有初始逻辑值的二进制刺激信号来完成。 动态平衡状态可以基于在刺激信号的两个连续转换周期内所采用的晶体管的浮动基板中的电荷量的变化平方和的精度误差内的抵消。

公开(公告)号：US20040047414A1

公开(公告)日：2004-03-11

申请号：US10465532

申请日：2003-06-19

Applicant: STMicroelectronics SA ,  STMicroelectronics N.V.

Inventor： Didier Helal ,  Fritz Lebowsky

IPC: H03K007/04 ,  H03K007/06

CPC classification number: H04B1/7174 ,  H03K7/04 ,  H04L25/4902

Abstract: A controllable pulse generator generates the pulses of the signal which are respectively contained in successive time windows, and a control device formulates a control signal for the generator including, for each pulse, an indication of its position in the corresponding window. The control device includes a processor to deliver for each time window, at a delivery frequency Fe greater than the pulse repetition frequency, successive groups of N bits together defining a digital cue of position of a pulse inside the window. Also, a converter converts this digital position cue into the control signal temporally spread over the length (T) of the window and including the indication of position at an instant corresponding to the digital position cue. This makes it possible to position the pulse inside its window with a temporal precision equal to 1/N.Fe.

Abstract translation: 可控脉冲发生器产生分别包含在连续时间窗口中的信号脉冲，并且控制装置为发生器制定一个控制信号，包括对于每个脉冲，其对应的窗口中其位置的指示。 控制装置包括处理器，用于以大于脉冲重复频率的传送频率Fe传送每个时间窗口，连续的N位组一起定义窗口内的脉冲位置的数字提示。 此外，转换器将该数字位置提示转换成在窗口的长度（T）上暂时分布的控制信号，并且包括在对应于数字位置提示的时刻的位置指示。 这使得可以将脉冲定位在其窗口内，时间精度等于1 / N.Fe。

公开(公告)号：US20040017722A1

公开(公告)日：2004-01-29

申请号：US10438733

申请日：2003-05-15

Applicant: STMicroelectronics SA

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink ,  Jean Devin

IPC: G11C007/00

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/3418

Abstract: The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.

公开(公告)号：US20020171494A1

公开(公告)日：2002-11-21

申请号：US10102402

申请日：2002-03-19

Applicant: STMicroelectronics, SA

Inventor： Pascal Debaty

IPC: H03F001/14

CPC classification number: H03F1/083

Abstract: A circuit for splitting poles between a first stage and a second inverting voltage-amplifier stage of an electronic circuit, comprises, in series between the output of the first stage and the output of the second stage, and in that order, a first capacitor, a second capacitor and a resistor. The circuit further comprises a voltage-divider bridge which is connected between a terminal delivering a substantially constant voltage and the output of the first stage. The output of the voltage-divider bridge is linked to the common node between the first capacitor and the second capacitor, in such a way that a first resistor of the voltage-divider bridge is connected in parallel with the first capacitor.

Abstract translation: 用于在电子电路的第一级和第二反相电压放大器级之间分离极的电路包括串联在第一级的输出和第二级的输出之间，并且依次包括第一电容器， 第二电容器和电阻器。 该电路还包括分压器桥，该分压器桥连接在提供基本上恒定的电压的端子和第一级的输出之间。 分压器桥的输出端连接到第一电容器和第二电容器之间的公共节点，使得分压器桥的第一电阻器与第一电容器并联连接。

公开(公告)号：US20010025344A1

公开(公告)日：2001-09-27

申请号：US09738548

申请日：2000-12-15

Applicant: STMicroelectronics SA.

Inventor： Yannick Teglia

IPC: G06F011/30

CPC classification number: G06F21/6218 ,  G06F21/755 ,  G06F2207/7219 ,  G06F2221/2123

Abstract: A method is provided for secured transfer of data from a first memory containing the data element to a second memory through a data bus that is connected between the first memory and the second memory. According to the method, a secret N-byte data element is transferred byte-by-byte through the data bus, with each byte transiting at least once on the data bus. Before each transfer of a byte of the secret data element, a current index ranging from 0 to Nnull1 is randomly chosen, with the current index corresponding to a place value of the byte to be transferred. At each transfer of a byte of the secret data element with a place value equal to the current index, a corresponding bit of an N-byte loading indicator is modified as a function of a loading mode, with the loading mode being an integer ranging from 0 to a first constant. The transfer of the secret data element is ended when the loading indicator takes a predetermined value.

Abstract translation: 提供了一种通过连接在第一存储器和第二存储器之间的数据总线将数据从包含数据元素的第一存储器安全地传送到第二存储器的方法。 根据该方法，秘密的N字节数据元素通过数据总线逐字节传送，每个字节在数据总线上至少一次传输一次。 在秘密数据元素的一个字节的每次传送之前，随机选择范围从0到N-1的当前索引，其中当前索引对应于要传送的字节的位置值。 在每个传输具有等于当前索引的位置值的秘密数据元素的一个字节的字节时，N字节加载指示符的相应位被修改为加载模式的函数，其中加载模式是从 0到第一个常数。 当加载指示符取预定值时，秘密数据元素的传送结束。