Delay circuit and related method thereof
    61.
    发明授权
    Delay circuit and related method thereof 有权
    延迟电路及其相关方法

    公开(公告)号:US07830192B2

    公开(公告)日:2010-11-09

    申请号:US12553963

    申请日:2009-09-03

    CPC classification number: H03K5/135 H03K2005/0011

    Abstract: A delay circuit comprising a delay measurement unit, a delay mapping unit and a map delay module. The delay measurement unit generates a mapping table according to a reference signal and a reference clock signal. The delay mapping unit generates a mapped delay selection signal according to an input selection signal and at least a mapping value from the mapping table. The map delay module delays an input data signal to generate an output data signal according to the mapped delay selection signal.

    Abstract translation: 一种延迟电路,包括延迟测量单元,延迟映射单元和地图延迟模块。 延迟测量单元根据参考信号和参考时钟信号生成映射表。 延迟映射单元根据输入选择信号产生映射延迟选择信号,并至少映射映射值。 映射延迟模块根据所映射的延迟选择信号延迟输入数据信号以产生输出数据信号。

    VIDEO COMPRESSION CIRCUIT AND METHOD THEREOF
    62.
    发明申请
    VIDEO COMPRESSION CIRCUIT AND METHOD THEREOF 有权
    视频压缩电路及其方法

    公开(公告)号:US20100232513A1

    公开(公告)日:2010-09-16

    申请号:US12608012

    申请日:2009-10-29

    CPC classification number: H04N19/85 H04N19/176 H04N19/426 H04N19/433 H04N19/61

    Abstract: A video compression circuit including a video pre-processor, a macroblock data storage unit and a video processor is provided. When fulfilled by an input video signal, the video pre-processor converts the input video signal to generate a macroblock data. The macroblock data storage unit alternatively and temporally stores the macroblock data generated from the video pre-processor. The video processor alternatively reads the macroblock data stored in the macroblock data storage unit, and compresses the readout macroblock data to an output video signal.

    Abstract translation: 提供了包括视频预处理器,宏块数据存储单元和视频处理器的视频压缩电路。 当通过输入视频信号来实现时,视频预处理器转换输入视频信号以产生宏块数据。 宏块数据存储单元交替地和临时地存储从视频预处理器生成的宏块数据。 视频处理器交替地读取存储在宏块数据存储单元中的宏块数据,并将读出的宏块数据压缩为输出视频信号。

    Tartrate Salt of (7S)-7-[(5-Fluoro-2-Methyl-Benzyl)oxy]-2-[(2R)-2-Methylpiperazin-1-YL]-6,7-Dihydro-5H-Cyclopenta[B]Pyridine
    63.
    发明申请
    Tartrate Salt of (7S)-7-[(5-Fluoro-2-Methyl-Benzyl)oxy]-2-[(2R)-2-Methylpiperazin-1-YL]-6,7-Dihydro-5H-Cyclopenta[B]Pyridine 审中-公开
    (7S)-7 - [(5-氟-2-甲基 - 苄基)氧基] -2 - [(2R)-2-甲基哌嗪-1-基] -6,7-二氢-5H-环戊二烯并[ B]吡啶

    公开(公告)号:US20100004259A1

    公开(公告)日:2010-01-07

    申请号:US12373774

    申请日:2008-01-24

    CPC classification number: C07D221/04

    Abstract: The present invention provides a tartrate salt of Formula (I), Formula I is also known as (7S)-7-[(5-fluoro-2-methyl-benzyl)oxy]-2-[(2R)-2-methylpiperazin-1-yl]-6,7-dihydro-5H-cyclopenta[b]pyridine. The tartrate salt is preferably crystalline. The tartrate salt of Formula I of the invention is useful in the treatment of diseases linked to activation of the 5HT2c receptor in animals including humans, for example, in the treatment of schizophrenia, cognitive deficits including cognitive deficits associated with schizophrenia, anxiety, depression, obsessive-compulsive disorder, epilepsy, obesity, sexual dysfunction, and urinary incontinence, among others.

    Abstract translation: 本发明提供式(I)的酒石酸盐,式I也称为(7S)-7 - [(5-氟-2-甲基 - 苄基)氧基] -2 - [(2R)-2-甲基哌嗪 -1-基] -6,7-二氢-5H-环戊二烯并[b]吡啶。 酒石酸盐优选是结晶的。 本发明的式I的酒石酸盐可用于治疗与包括人在内的动物中的5HT2c受体活化相关的疾病,例如精神分裂症的治疗,认知缺陷,包括与精神分裂症相关的认知缺陷,焦虑,抑郁, 强迫症,癫痫,肥胖,性功能障碍和尿失禁等。

    DELAY CIRCUIT AND RELATED METHOD THEREOF
    64.
    发明申请
    DELAY CIRCUIT AND RELATED METHOD THEREOF 有权
    延迟电路及其相关方法

    公开(公告)号:US20090322397A1

    公开(公告)日:2009-12-31

    申请号:US12553963

    申请日:2009-09-03

    CPC classification number: H03K5/135 H03K2005/0011

    Abstract: A delay circuit comprising a delay measurement unit, a delay mapping unit and a map delay module. The delay measurement unit generates a mapping table according to a reference signal and a reference clock signal. The delay mapping unit generates a mapped delay selection signal according to an input selection signal and at least a mapping value from the mapping table. The map delay module delays an input data signal to generate an output data signal according to the mapped delay selection signal.

    Abstract translation: 一种延迟电路,包括延迟测量单元,延迟映射单元和地图延迟模块。 延迟测量单元根据参考信号和参考时钟信号生成映射表。 延迟映射单元根据输入选择信号产生映射延迟选择信号,并至少映射映射值。 映射延迟模块根据所映射的延迟选择信号延迟输入数据信号以产生输出数据信号。

    ADHESIVE TAPE CUTTER
    65.
    发明申请
    ADHESIVE TAPE CUTTER 失效
    胶带切割机

    公开(公告)号:US20090301660A1

    公开(公告)日:2009-12-10

    申请号:US12172272

    申请日:2008-07-14

    Applicant: Yu Chin Liu

    Inventor: Yu Chin Liu

    CPC classification number: B65H35/0026 Y10T156/1365

    Abstract: An adhesive tape cutter comprising a pair of protecting portions formed in pair at the right and left sides for fitting and cutting an adhesive tape roll. The top of the protecting portions includes a tape-guiding slot and a tape-attaching portion while a slide slot portion is formed at a side wall of the protecting portions. The slide cap is fitted with a cutting edge, and the slide cap further includes a sliding piece that fits into the slide slot portion in such a manner that a proper sliding action is achieved. An elastic supporting piece is integrally formed within a tape-receiving space defined by the protecting portions such that that the elastic supporting piece can be pushed against the adhesive tape roll at any time. In this way, a certain clamping relationship between the adhesive tape roll and the protecting portions is constantly maintained.

    Abstract translation: 一种胶带切割机,包括一对在左右两侧形成的用于装配和切割胶带的保护部分。 保护部分的顶部包括带引导槽和带附接部分,同时在保护部分的侧壁处形成滑槽部分。 滑动盖配有切割刃,滑盖还包括滑动件,该滑动件以能够实现适当的滑动动作的方式配合到滑槽部。 弹性支撑件一体地形成在由保护部限定的带容纳空间内,使得弹性支撑件可以随时被推靠在胶带卷上。 以这种方式,不断地保持胶带卷与保护部之间的一定的夹紧关系。

    Magnetomechanical tag used in electronic article surveillance and method of manufacturing a magnetomechanical tag
    66.
    发明授权
    Magnetomechanical tag used in electronic article surveillance and method of manufacturing a magnetomechanical tag 有权
    用于电子物品监控的磁力机械标签和制造磁力机械标签的方法

    公开(公告)号:US07623039B2

    公开(公告)日:2009-11-24

    申请号:US11493410

    申请日:2006-07-25

    Applicant: Nen-Chin Liu

    Inventor: Nen-Chin Liu

    CPC classification number: G08B13/2437 G08B13/2408

    Abstract: A magnetomechanical tag for use in an electronic article surveillance (EAS) system and a method of manufacturing the magnetomechanical tag may be provided. The EAS may include at least one resonator, a housing configured to allow vibration therein of the at least one resonator and a cover heat sealed to the housing at a heat sealing temperature. The EAS tag further may include a powder lubricant within the housing. The powder lubricant may have a melting temperature less the heat sealing temperature.

    Abstract translation: 可以提供用于电子物品监视(EAS)系统的磁力机械标签和制造磁力机械标签的方法。 EAS可以包括至少一个谐振器,被配置为允许至少一个谐振器的振动的壳体和在热封温度下密封到壳体的盖。 EAS标签还可以包括在壳体内的粉末润滑剂。 粉末润滑剂的熔化温度可以低于热封温度。

    SEMICONDUCTOR DEVICES, INTEGRATED CIRCUIT PACKAGES AND TESTING METHODS THEREOF
    67.
    发明申请
    SEMICONDUCTOR DEVICES, INTEGRATED CIRCUIT PACKAGES AND TESTING METHODS THEREOF 审中-公开
    半导体器件,集成电路封装及其测试方法

    公开(公告)号:US20090265596A1

    公开(公告)日:2009-10-22

    申请号:US12107166

    申请日:2008-04-22

    Abstract: An integrated circuit package comprising a semiconductor device and pins is provided. The semiconductor device comprises first and second scan chains, each having an input port and an output port. The semiconductor device further comprises at least two first pads, at least two second pads, and a connecting device. The at least two first pads are coupled to the input port of the first scan chain and the output port of the second scan chain, respectively. The at least two second pads are coupled to the output port of the first scan chain and the input port of the second scan chain, respectively. The connecting device is coupled between the first and the second chains, and is capable of controlling electrical connection between the input port of the second scan chain and the output port of the first scan chain. When the connecting device is disabled, the input port of the second scan chain is electrically disconnected from the output port of the first scan chain. The first pads are electrically connected to the pins and the second pads are not electrically connected to any pins of the integrated circuit package.

    Abstract translation: 提供了包括半导体器件和引脚的集成电路封装。 该半导体器件包括第一和第二扫描链,每个具有输入端口和输出端口。 半导体器件还包括至少两个第一焊盘,至少两个第二焊盘和连接装置。 所述至少两个第一焊盘分别耦合到第一扫描链的输入端口和第二扫描链的输出端口。 所述至少两个第二焊盘分别耦合到第一扫描链的输出端口和第二扫描链的输入端口。 连接装置耦合在第一和第二链之间,并且能够控制第二扫描链的输入端口和第一扫描链的输出端口之间的电连接。 当禁用连接设备时,第二扫描链的输入端口与第一扫描链的输出端口电断开。 第一焊盘电连接到引脚,并且第二焊盘不电连接到集成电路封装的任何引脚。

    LEVEL SHIFTERS
    68.
    发明申请
    LEVEL SHIFTERS 有权
    水平移位

    公开(公告)号:US20090096484A1

    公开(公告)日:2009-04-16

    申请号:US11871234

    申请日:2007-10-12

    CPC classification number: H03K3/356113 H03K3/356182

    Abstract: Level shifters capable of setting logic level of the output signals thereof to a pre-defined known state during power-up are provided, in which a first logic unit is powered by a first power voltage, receives input signals with a core power voltage and comprises first and second output terminals. First and second drivers are coupled between the first output terminal and the first power voltage and between the second output terminal and the second power voltage respectively. When one of the first and second power voltages is not ready during power-up, the first driver matches a voltage level on the first output terminal with the first power voltage by AC coupling and the second driver pulls low or maintains a voltage level on the second output terminal.

    Abstract translation: 提供能够将其输出信号的逻辑电平设置为上电期间的预定已知状态的电平移位器,其中第一逻辑单元由第一电源电压供电,接收具有核心电源电压的输入信号,并且包括 第一和第二输出端子。 第一和第二驱动器分别耦合在第一输出端和第一电源电压之间以及第二输出端和第二电源电压之间。 当在上电期间第一和第二电源电压之一未准备好时,第一驱动器通过AC耦合将第一输出端子上的电压与第一电源电压相匹配,并且第二驱动器拉低电压或维持电压电平 第二输出端子。

    Write signal control circuit in an optical disk drive
    69.
    发明授权
    Write signal control circuit in an optical disk drive 失效
    在光盘驱动器中写入信号控制电路

    公开(公告)号:US07471599B2

    公开(公告)日:2008-12-30

    申请号:US10880533

    申请日:2004-07-01

    CPC classification number: G11B7/00456 G11B7/1267

    Abstract: A write signal control circuit in an optical disk drive for adjusting the duty cycle of the write signals by a duty cycle adjusting unit. The write signal control circuit includes a write signal generator for converting an EFM signal into the write signals according to the write strategy waveform generating rules, a duty cycle adjusting unit for adjusting the duty cycle of each write signal according to adjusting parameters and for outputting adjusted write signals, and a duty cycle detector for detecting the duty cycle of each adjusted write signal and outputting a respective duty cycle control signal. The duty cycle adjusting unit further receives the duty cycle control signal to adapt the adjusting parameters.

    Abstract translation: 一种光盘驱动器中的写入信号控制电路,用于通过占空比调节单元来调整写入信号的占空比。 写入信号控制电路包括写入信号发生器,用于根据写入策略波形生成规则将EFM信号转换成写入信号;占空比调整单元,用于根据调整参数调整每个写入信号的占空比, 写入信号,以及占空比检测器,用于检测每个经调整的写信号的占空比并输出相应的占空比控制信号。 占空比调整单元还接收占空比控制信号以适应调整参数。

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