公开(公告)号：US12125737B1

公开(公告)日：2024-10-22

申请号：US18736423

申请日：2024-06-06

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

公开(公告)号：US11923230B1

公开(公告)日：2024-03-05

申请号：US18382468

申请日：2023-10-20

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H10B20/20

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.

公开(公告)号：US11699632B2

公开(公告)日：2023-07-11

申请号：US17153706

申请日：2021-01-20

申请人： ALPHA ASSEMBLY SOLUTIONS INC.

发明人： Monnir Boureghda ,  Nitin Desai ,  Anna Lifton ,  Oscar Khaselev ,  Michael T. Marczi ,  Bawa Singh

IPC分类号： H05K13/04 ,  H01L23/373 ,  H01L23/00

CPC分类号： H01L23/373 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H05K13/0465 ,  H01L2224/2936 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/32225 ,  H01L2224/8384 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2924/0102 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/203 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49155 ,  Y10T428/24893 ,  H01L2224/29101 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/0132 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29111 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2224/83192 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/203 ,  H01L2924/0002

摘要： Methods for attachment and devices produced using such methods are disclosed. In certain examples, the method comprises disposing a capped nanomaterial on a substrate, disposing a die on the disposed capped nanomaterial, drying the disposed capped nanomaterial and the disposed die, and sintering the dried disposed die and the dried capped nanomaterial at a temperature of 300° C. or less to attach the die to the substrate. Devices produced using the methods are also described.

公开(公告)号：US20190131172A1

公开(公告)日：2019-05-02

申请号：US16227752

申请日：2018-12-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC分类号： H01L21/768 ,  H01L21/683 ,  H01L23/48 ,  H01L23/00 ,  H01L23/544

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00

摘要： A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

公开(公告)号：US20180331071A1

公开(公告)日：2018-11-15

申请号：US15971600

申请日：2018-05-04

申请人： Samsung Electronics Co., Ltd.

发明人： Heung-Kyu KWON ,  Min-Ok NA ,  Sung-Woo PARK ,  Ji-Hyun PARK ,  Su-Min PARK

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L25/18 ,  H01L25/10 ,  H01L23/552

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01064 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

公开(公告)号：US09881999B2

公开(公告)日：2018-01-30

申请号：US12488310

申请日：2009-06-19

申请人： Arun Majumdar ,  Ali Shakouri ,  Timothy D. Sands ,  Peidong Yang ,  Samuel S. Mao ,  Richard E. Russo ,  Henning Feick ,  Eicke R. Weber ,  Hannes Kind ,  Michael Huang ,  Haoquan Yan ,  Yiying Wu ,  Rong Fan

发明人： Arun Majumdar ,  Ali Shakouri ,  Timothy D. Sands ,  Peidong Yang ,  Samuel S. Mao ,  Richard E. Russo ,  Henning Feick ,  Eicke R. Weber ,  Hannes Kind ,  Michael Huang ,  Haoquan Yan ,  Yiying Wu ,  Rong Fan

IPC分类号： B32B5/02 ,  B32B9/00 ,  H01L29/06 ,  B82Y10/00 ,  B82Y20/00 ,  G02B6/10 ,  H01L21/02 ,  H01L23/00 ,  H01L29/12 ,  H01L31/0352 ,  H01L33/06 ,  H01L33/24 ,  H01L35/00 ,  H01L41/18 ,  H01L41/09 ,  H01L33/18 ,  H01S5/34

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y20/00 ,  G02B6/107 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02554 ,  H01L21/02603 ,  H01L21/02645 ,  H01L21/02653 ,  H01L24/45 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/12 ,  H01L29/125 ,  H01L31/0352 ,  H01L33/06 ,  H01L33/18 ,  H01L33/24 ,  H01L35/00 ,  H01L41/094 ,  H01L41/18 ,  H01L41/183 ,  H01L2224/45565 ,  H01L2224/45599 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01084 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01S5/341 ,  H01S5/3412 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764 ,  Y10S977/765 ,  Y10S977/951 ,  Y10T428/24994 ,  Y10T428/249949 ,  Y10T428/29 ,  Y10T428/2913 ,  Y10T428/2916 ,  Y10T428/292 ,  Y10T428/2933 ,  Y10T428/2958 ,  Y10T428/2973 ,  Y10T428/298 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/48

摘要： One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

公开(公告)号：US09852940B2

公开(公告)日：2017-12-26

申请号：US13756427

申请日：2013-01-31

申请人： Infineon Technologies Americas Corp.

发明人： Martin Standing ,  Andrew Sawle ,  Matthew P. Elwin ,  David P. Jones ,  Martin Carroll ,  Ian Glenville Wagstaffe

IPC分类号： H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L21/76829 ,  H01L23/3171 ,  H01L23/498 ,  H01L24/05 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05552

摘要： A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.

公开(公告)号：US20170200689A1

公开(公告)日：2017-07-13

申请号：US15107421

申请日：2015-07-22

申请人： NIPPON MICROMETAL CORPORATION ,  NIPPON STEEL & SUMIKIN MATERIALS CO., LTD.

发明人： Takashi YAMADA ,  Daizo ODA ,  Teruo HAIBARA ,  Ryo OISHI ,  Kazuyuki SAITO ,  Tomohiro UNO

IPC分类号： H01L23/00 ,  C22C9/04 ,  C22C9/06 ,  B23K35/02 ,  B23K35/30

CPC分类号： B23K35/0227 ,  B23K35/3013 ,  B23K35/302 ,  B23K2101/40 ,  B32B15/00 ,  B32B15/01 ,  B32B15/018 ,  C22C5/04 ,  C22C9/00 ,  C22C9/04 ,  C22C9/06 ,  C23C30/00 ,  C23C30/005 ,  H01L24/05 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05624 ,  H01L2224/43 ,  H01L2224/4312 ,  H01L2224/43125 ,  H01L2224/4321 ,  H01L2224/4382 ,  H01L2224/43848 ,  H01L2224/43986 ,  H01L2224/45 ,  H01L2224/45005 ,  H01L2224/45015 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45113 ,  H01L2224/45118 ,  H01L2224/4512 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/45178 ,  H01L2224/45541 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/48824 ,  H01L2224/78 ,  H01L2224/78251 ,  H01L2224/85 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85203 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01034 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/0665 ,  H01L2924/0705 ,  H01L2924/10253 ,  H01L2924/186 ,  Y10T428/12868 ,  Y10T428/12875 ,  Y10T428/12882 ,  Y10T428/12889 ,  Y10T428/12896 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/2495 ,  Y10T428/24967 ,  Y10T428/265 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/01045 ,  H01L2924/01049 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01031 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/01029 ,  H01L2924/01202 ,  H01L2924/01203 ,  H01L2924/01204 ,  H01L2924/00015 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/20752 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/20105 ,  H01L2924/01001 ,  H01L2924/01007 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01027 ,  H01L2924/01047 ,  H01L2924/01013

摘要： A bonding wire includes a Cu alloy core material, and a Pd coating layer formed on the Cu alloy core material. The bonding wire contains at least one element selected from Ni, Zn, Rh, In, Ir, and Pt. A concentration of the elements in total relative to the entire wire is 0.03% by mass or more and 2% by mass or less. When measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation angled at 15 degrees or less to a wire axis direction has a proportion of 50% or more among crystal orientations in the wire axis direction. An average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 μm or more and 1.3 μm or less.

公开(公告)号：US20170092554A1

公开(公告)日：2017-03-30

申请号：US15378420

申请日：2016-12-14

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Yoshiyuki ABE ,  Chuichi MIYAZAKI ,  Hideo MUTOU ,  Tomoko HIGASHINO

IPC分类号： H01L21/66 ,  H01L21/78 ,  H01L21/268 ,  H01L21/683 ,  B23K26/53 ,  H01L21/48 ,  H01L21/56 ,  H01L21/67 ,  H01L25/065 ,  B23K26/00 ,  H01L23/544 ,  H01L21/304

CPC分类号： H01L22/32 ,  B23K26/0006 ,  B23K26/40 ,  B23K26/53 ,  B23K2101/40 ,  B23K2103/50 ,  B23K2103/56 ,  H01L21/268 ,  H01L21/304 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/67092 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/6838 ,  H01L21/78 ,  H01L22/12 ,  H01L22/34 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/065 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2223/5448 ,  H01L2224/02235 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.

公开(公告)号：US20170084564A1

公开(公告)日：2017-03-23

申请号：US15369815

申请日：2016-12-05

申请人： Intel Corporation

发明人： Valery M. DUBIN ,  Sridhar BALAKRISHNAN ,  Mark BOHR

IPC分类号： H01L23/00 ,  H01L21/48

CPC分类号： H01L24/13 ,  H01L21/288 ,  H01L21/4853 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11614 ,  H01L2224/13026 ,  H01L2224/13084 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13564 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/29111 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.