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公开(公告)号：US20090096484A1
公开(公告)日：2009-04-16
申请号：US11871234
申请日：2007-10-12
申请人： Che Yuan Jao , Yuan-Chin Liu
发明人： Che Yuan Jao , Yuan-Chin Liu
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/356182
摘要： Level shifters capable of setting logic level of the output signals thereof to a pre-defined known state during power-up are provided, in which a first logic unit is powered by a first power voltage, receives input signals with a core power voltage and comprises first and second output terminals. First and second drivers are coupled between the first output terminal and the first power voltage and between the second output terminal and the second power voltage respectively. When one of the first and second power voltages is not ready during power-up, the first driver matches a voltage level on the first output terminal with the first power voltage by AC coupling and the second driver pulls low or maintains a voltage level on the second output terminal.
摘要翻译： 提供能够将其输出信号的逻辑电平设置为上电期间的预定已知状态的电平移位器，其中第一逻辑单元由第一电源电压供电，接收具有核心电源电压的输入信号，并且包括 第一和第二输出端子。 第一和第二驱动器分别耦合在第一输出端和第一电源电压之间以及第二输出端和第二电源电压之间。 当在上电期间第一和第二电源电压之一未准备好时，第一驱动器通过AC耦合将第一输出端子上的电压与第一电源电压相匹配，并且第二驱动器拉低电压或维持电压电平 第二输出端子。
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公开(公告)号：US07804327B2
公开(公告)日：2010-09-28
申请号：US11871234
申请日：2007-10-12
申请人： Che Yuan Jao , Yuan-Chin Liu
发明人： Che Yuan Jao , Yuan-Chin Liu
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113 , H03K3/356182
摘要： Level shifters capable of setting logic level of the output signals thereof to a pre-defined known state during power-up are provided, in which a first logic unit is powered by a first power voltage, receives input signals with a core power voltage and comprises first and second output terminals. First and second drivers are coupled between the first output terminal and the first power voltage and between the second output terminal and the second power voltage respectively. When one of the first and second power voltages is not ready during power-up, the first driver matches a voltage level on the first output terminal with the first power voltage by AC coupling and the second driver pulls low or maintains a voltage level on the second output terminal.
摘要翻译： 提供能够将其输出信号的逻辑电平设置为上电期间的预定已知状态的电平移位器，其中第一逻辑单元由第一电源电压供电，接收具有核心电源电压的输入信号，并且包括 第一和第二输出端子。 第一和第二驱动器分别耦合在第一输出端和第一电源电压之间以及第二输出端和第二电源电压之间。 当在上电期间第一和第二电源电压之一未准备好时，第一驱动器通过AC耦合将第一输出端子上的电压与第一电源电压相匹配，并且第二驱动器拉低电压或维持电压电平 第二输出端子。
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公开(公告)号：US20090187874A1
公开(公告)日：2009-07-23
申请号：US12015627
申请日：2008-01-17
申请人： Mao-Lin Wu , Shih-Hung Lin , Hua Wu , Che Yuan Jao , Ching-Chih Li , Sheng-Ming Chang
发明人： Mao-Lin Wu , Shih-Hung Lin , Hua Wu , Che Yuan Jao , Ching-Chih Li , Sheng-Ming Chang
IPC分类号： G06F17/50
CPC分类号： H05K1/0216 , H01R12/79 , H05K1/0237 , H05K2201/09236 , H05K2201/10166 , H05K2201/10689
摘要： A circuit and a circuit design method are provided. The circuit operates between a first power source voltage and a ground voltage. The circuit comprises at least one low speed circuit path and at least one high speed circuit path. The low speed circuit path adjusts voltage level at the first power source voltage or the ground voltage. The low speed circuit path provides a first return path and isolates unwanted noise signals for a signal on the high speed circuit path.
摘要翻译： 提供电路和电路设计方法。 该电路在第一电源电压和接地电压之间工作。 该电路包括至少一个低速电路路径和至少一个高速电路路径。 低速电路路径调整第一电源电压或接地电压时的电压电平。 低速电路路径提供第一返回路径并隔离高速电路路径上的信号的不需要的噪声信号。
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公开(公告)号：US20080068910A1
公开(公告)日：2008-03-20
申请号：US11869196
申请日：2007-10-09
申请人： Che Yuan Jao
发明人： Che Yuan Jao
IPC分类号： G11C7/02
摘要： Memory circuits capable of preventing false programming caused by power-up sequence are provided, in which a programmable unit comprises a plurality of programmable elements, a source bus coupled between an external programming voltage and the programmable elements, a switching unit connected between the external programming voltage and the source bus, comprising a control terminal, and a level shifter, shifting a voltage level of an enabling signal to a first power voltage from a second power voltage lower than the external programming voltage. When the second power voltage is not ready during power up, the level shifter sets the control terminal of the switching unit to a predetermined logic level such that the switching unit is turned off and the source bus is disconnected from the external programming voltage thereby preventing false programming.
摘要翻译： 提供了能够防止由上电序列引起的伪编程的存储器电路，其中可编程单元包括多个可编程元件，耦合在外部编程电压和可编程元件之间的源极总线，连接在外部编程 电压和源极总线，包括控制端子和电平移位器，使能信号的电压电平从低于外部编程电压的第二电源电压移位到第一电源电压。 当上电期间第二电源电压未准备好时，电平移位器将开关单元的控制端子设置为预定的逻辑电平，使得开关单元断开，并且源总线与外部编程电压断开，从而防止错误 编程。
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公开(公告)号：US07741855B2
公开(公告)日：2010-06-22
申请号：US12336491
申请日：2008-12-16
申请人： Che Yuan Jao
发明人： Che Yuan Jao
CPC分类号： H03H11/30 , H03H11/245 , H04L25/0278 , H04L25/0298
摘要： A calibration circuit including a plurality of first resistance components, a plurality of second resistance components, and a first feedback system is provided. The first feedback system selects M1 first resistance components and N1 second resistance components so that a first combination of the M1 first resistance components and the N1 second resistance components has a first predetermined relationship with the impedance of a first resistor. The first feedback system selects M2 first resistance components and N2 second resistance components so that a second combination of the M2 first resistance components and the N2 second resistance components has a second predetermined relationship with the impedance of the first resistor. Based on the values of M1, N1, M2, N2, and a target impedance, the first feedback system generates a first set of calibration signals for a plurality of third resistance components and generates a second set of calibration signals for a plurality of fourth resistance components.
摘要翻译： 提供了包括多个第一电阻分量，多个第二电阻分量和第一反馈系统的校准电路。 第一反馈系统选择M1第一电阻分量和N1第二电阻分量，使得M1第一电阻分量和N1第二电阻分量的第一组合与第一电阻器的阻抗具有第一预定关系。 第一反馈系统选择M2第一电阻分量和N2第二电阻分量，使得M2第一电阻分量和N2第二电阻分量的第二组合与第一电阻器的阻抗具有第二预定关系。 基于M1，N1，M2，N2和目标阻抗的值，第一反馈系统为多个第三电阻分量产生第一组校准信号，并产生用于多个第四电阻的第二组校准信号 组件。
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公开(公告)号：US07755384B2
公开(公告)日：2010-07-13
申请号：US12212906
申请日：2008-09-18
申请人： Che Yuan Jao
发明人： Che Yuan Jao
IPC分类号： H03K19/003
CPC分类号： H03K19/018592 , H03K19/0005 , H04L5/1461 , H04L25/0278
摘要： A bi-directional buffer is provided. The buffer includes a driver, a receiver, and a circuitry configured to select a driving mode in response to detecting a first condition and to select a receiving mode in response to detecting a second condition. The driving mode has a first impedance and the receiving mode has a second impedance. The second impedance is partially contributed from the driver.
摘要翻译： 提供双向缓冲器。 缓冲器包括驱动器，接收器和被配置为响应于检测到第一状况而选择驱动模式并且响应于检测到第二状况而选择接收模式的电路。 驱动模式具有第一阻抗，并且接收模式具有第二阻抗。 第二阻抗部分地由驾驶员贡献。
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公开(公告)号：US07486085B2
公开(公告)日：2009-02-03
申请号：US11698517
申请日：2007-01-25
申请人： Che Yuan Jao
发明人： Che Yuan Jao
CPC分类号： H03H11/30 , H03H11/245 , H04L25/0278 , H04L25/0298
摘要： A calibration circuit including a plurality of first resistance components, a plurality of second resistance components, and a first feedback system is provided. The first feedback system selects M1 first resistance components and N1 second resistance components so that a first combination of the M1 first resistance components and the N1 second resistance components substantially matches the impedance of a first resistor. The first feedback system selects M2 first resistance components and N2 second resistance components so that a second combination of the M2 first resistance components and the N2 second resistance components substantially matches the impedance of the first resistor. Based on the values of M1, N1, M2, N2, and a target impedance, the first feedback system generates a first set of calibration signals for a plurality of third resistance components and generates a second set of calibration signals for a plurality of fourth resistance components.
摘要翻译： 提供了包括多个第一电阻分量，多个第二电阻分量和第一反馈系统的校准电路。 第一反馈系统选择M1第一电阻分量和N1第二电阻分量，使得M1第一电阻分量和N1第二电阻分量的第一组合基本上匹配第一电阻器的阻抗。 第一反馈系统选择M2第一电阻分量和N2第二电阻分量，使得M2第一电阻分量和N2第二电阻分量的第二组合基本上匹配第一电阻器的阻抗。 基于M1，N1，M2，N2和目标阻抗的值，第一反馈系统为多个第三电阻分量产生第一组校准信号，并产生用于多个第四电阻的第二组校准信号 组件。
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