公开(公告)号：US6033963A

公开(公告)日：2000-03-07

申请号：US385523

申请日：1999-08-30

Applicant: Jenn Ming Huang ,  Chi-Wen Su ,  Chung-Cheng Wu ,  Shui-Hung Chen

Inventor： Jenn Ming Huang ,  Chi-Wen Su ,  Chung-Cheng Wu ,  Shui-Hung Chen

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/49

CPC classification number: H01L29/6659 ,  H01L21/76838 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method of forming a metal gate for a CMOS device using a replacement gate process wherein sidewall spacers are formed on a dummy electrode prior to forming the metal gate allowing source and drain formation prior to metal gate formation and a tungsten layer is selectively deposited to act as an each or CMP stop and to reduce source and drain resistance. The process begins by forming a dummy gate oxide layer and a polysilicon dummy gate electrode layer on a substrate structure and patterning them to form a dummy gate. Lightly doped source and drain regions are formed by ion implantation using the dummy gate as an implant mask. Spacers are formed on the sidewalls of the dummy gate. Source and drain regions are formed by implanting ions using,the dummy gate and spacers as an implant mask and performing a rapid thermal anneal. A tungsten layer is selectively deposited on the dummy gate electrode and the source and drain regions. A blanket dielectric layer is formed over the dummy gate and the substrate structure. The blanket dielectric layer is planarized using a chemical mechanical polishing process stopping on the tungsten layer. The tungsten layer overlying the dummy gate and the dummy gate are removed, thereby forming a gate opening. A gate oxide layer and a metal gate electrode layer are formed in the gate opening. The gate electrode layer is planarized to form a metal gate, stopping on the blanket dielectric layer. Alternatively, the dummy gate electrode can be composed of silicon nitride and the selectively deposited tungsten layer can be omitted.

Abstract translation: 使用替代栅极工艺形成用于CMOS器件的金属栅极的方法，其中在形成金属栅极之前在虚设电极上形成侧壁间隔物，其允许在金属栅极形成之前的源极和漏极形成以及选择性地沉积钨层以起作用 作为每个或CMP停止并减少源极和漏极电阻。 该过程开始于在衬底结构上形成虚拟栅极氧化物层和多晶硅虚拟栅极电极层并将其图案化以形成虚拟栅极。 通过使用伪栅极作为注入掩模的离子注入形成轻掺杂源极和漏极区域。 隔板形成在虚拟门的侧壁上。 通过使用伪栅极和间隔物作为注入掩模注入离子并执行快速热退火来形成源区和漏区。 钨层被选择性地沉积在虚拟栅极电极和源极和漏极区域上。 在伪栅极和衬底结构之上形成覆盖层的介电层。 使用在钨层上停止的化学机械抛光工艺来平坦化覆盖绝缘层。 覆盖虚拟栅极和虚拟栅极的钨层被去除，从而形成栅极开口。 栅极氧化层和金属栅极电极层形成在栅极开口中。 栅极电极层被平坦化以形成金属栅极，停止在覆盖电介质层上。 或者，伪栅电极可以由氮化硅构成，并且可以省略选择性沉积的钨层。

公开(公告)号：US5726086A

公开(公告)日：1998-03-10

申请号：US746842

申请日：1996-11-18

Applicant: Chung-Cheng Wu

Inventor： Chung-Cheng Wu

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L27/10852 ,  H01L28/91

Abstract: The present invention discloses a method of fabricating self-aligned cylindrical capacitor in stack Dynamic Random Access Memory (Stack DRAM) cells. The polysilicon stud is filled in the contact window of the source region of a metal-oxide-semiconductor field effect transistor (MOSFET). Then the polysilicon spacers are formed on the sidewalls of the first polysilicon stud. The cylindrical capacitor storage node of the DRAM capacitor of the present invention has much greater surface area so as to increase the capacitance value of the DRAM capacitor, that can achieve high packing density of the integrated circuit devices. Furthermore, this new process only needs one lithography photomask to open contact window compared with the conventional process which needs two lithography photomasks, that further reduces the production cost.

Abstract translation: 本发明公开了一种在堆叠动态随机存取存储器（Stack DRAM）单元中制造自对准圆柱形电容器的方法。 多晶硅螺柱填充在金属氧化物半导体场效应晶体管（MOSFET）的源极区域的接触窗口中。 然后，多晶硅间隔物形成在第一多晶硅柱的侧壁上。 本发明的DRAM电容器的圆柱形电容器存储节点具有大得多的表面积，以便增加DRAM电容器的电容值，这可以实现集成电路器件的高封装密度。 此外，与需要两个光刻光掩模的常规工艺相比，该新工艺仅需要一个光刻光掩模来打开接触窗口，这进一步降低了生产成本。

公开(公告)号：US5650346A

公开(公告)日：1997-07-22

申请号：US557546

申请日：1995-11-14

Applicant: Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

Inventor： Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/11558

Abstract: A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by:forming between regions containing MOSFET devices a region with a plurality of bit lines in the substrate by ion implantation through the gate oxide into the substrate in a predetermined pattern and,forming a polysilicon electrode on the dielectric material crossing over the bit lines.

Abstract translation: 一种MOSFET器件，其具有覆盖有介电材料的衬底，该器件包括电容耦合到多晶硅电极的多个掩埋导体，其通过以下方式制成：在包含MOSFET器件的区域之间形成通过离子注入穿过衬底中的多个位线的区域 栅极氧化物以预定图案进入衬底，并且在电介质材料上形成跨越位线的多晶硅电极。

公开(公告)号：US5554545A

公开(公告)日：1996-09-10

申请号：US299266

申请日：1994-09-01

Applicant: Chung-Cheng Wu ,  Ming-Tzong Yang

Inventor： Chung-Cheng Wu ,  Ming-Tzong Yang

IPC: H01L21/822 ,  H01L27/115 ,  H01L21/265

CPC classification number: H01L27/115 ,  H01L21/8221 ,  H01L29/788 ,  Y10S148/116 ,  Y10S148/117 ,  Y10S148/163 ,  Y10S438/981

Abstract: An MOSFET device is fabricated with a plurality of conductors capacitively coupled to a first electrode, forming a mask on the surface of the first electrode exposing a predetermined zone of the first electrode, doping the first electrode through the mask, removing the mask from the surface of the first electrode, oxidizing the first electrode to form a layer of oxide over the first electrode with a thicker layer of oxide over the predetermined zone and a thinner layer of oxide elsewhere, forming at least one electrode over the first electrode on the thinner layer of oxide outside of the zone and forming at least one other electrode over the first electrode on the thicker layer of oxide inside the zone, whereby the one electrode and the other electrode have substantially different capacitive coupling to the electrode.

Abstract translation: 制造具有电容耦合到第一电极的多个导体的MOSFET器件，在第一电极的表面上形成掩模，暴露第一电极的预定区域，通过掩模掺杂第一电极，从表面去除掩模 在所述第一电极上氧化所述第一电极以在所述第一电极上形成氧化层以在所述预定区域上具有较厚的氧化物层，并且在其它地方形成更薄的氧化物层，在所述较薄层上的所述第一电极上形成至少一个电极 的氧化物，并且在所述区域内的更厚的氧化物层上在所述第一电极上方形成至少一个其它电极，由此所述一个电极和所述另一个电极具有与所述电极基本上不同的电容耦合。