公开(公告)号：US20100164605A1

公开(公告)日：2010-07-01

申请号：US12650592

申请日：2009-12-31

Applicant: Jun-Ho LEE ,  Hyung-Dong Lee ,  Hyun-Seok Kim

Inventor： Jun-Ho LEE ,  Hyung-Dong Lee ,  Hyun-Seok Kim

IPC: G05F1/10

CPC classification number: H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit is capable of minimizing/decreasing the increase in the inductance of a package due to a power supply network thereof. The semiconductor integrated circuit includes a first power mesh configured to supply a first power to a first internal circuit, a second power mesh configured to supply a second power to a second internal circuit, the first power and the second power being used for different purposes and being equal in DC level, and a connection unit configured to connect the first power mesh to the second power mesh.

Abstract translation: 半导体集成电路能够最小化/减少由于其电源网络而导致的封装的电感的增加。 半导体集成电路包括被配置为向第一内部电路提供第一功率的第一功率网格，被配置为将第二功率提供给第二内部电路的第二功率网，所述第一功率和所述第二功率用于不同的目的， 在DC电平上相等，以及连接单元，被配置为将第一电力网连接到第二电力网。

公开(公告)号：US20100164076A1

公开(公告)日：2010-07-01

申请号：US12346429

申请日：2008-12-30

Applicant: Jun-Ho Lee ,  Hyung-Dong Lee ,  Hyun-Seok Kim

Inventor： Jun-Ho Lee ,  Hyung-Dong Lee ,  Hyun-Seok Kim

IPC: H01L23/552 ,  H01L23/02

CPC classification number: H01L23/552 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor package includes a wire board, a plurality of semiconductor chips configured to be stacked over the wire board and to be electrically coupled with the wire board, and at least one shielding unit configured to be formed between the plurality of semiconductor chips and to be maintained at a predetermined voltage.

Abstract translation: 一种半导体封装，包括线路板，多个半导体芯片，被配置为堆叠在线路板上并与线路板电连接;以及至少一个屏蔽单元，被配置为形成在所述多个半导体芯片之间， 保持在预定电压。

公开(公告)号：US07579861B2

公开(公告)日：2009-08-25

申请号：US11906365

申请日：2007-10-01

Applicant: Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

Inventor： Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K19/00384

Abstract: An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.

Abstract translation: 阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测 信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有 一个预期的阻抗。

公开(公告)号：US20080079458A1

公开(公告)日：2008-04-03

申请号：US11906365

申请日：2007-10-01

Applicant: Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

Inventor： Dong-Suk Shin ,  Inhwa Jung ,  Chulwoo Kim ,  Hyung-Dong Lee ,  Young-Jung Choi

IPC: H03K19/0185

CPC classification number: H03K19/00384

Abstract: An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.

Abstract translation: 阻抗控制的伪开漏输出驱动电路包括：处理电压和温度（PVT）检测器，被配置为具有接收参考时钟的延迟线，并根据PVT条件检测延迟线的状态变化以输出检测 信号; 选择信号发生器，被配置为基于所述检测信号和输出数据产生驱动选择信号; 以及输出驱动器，被配置为驱动输出端子，所述输出驱动器包括由所述驱动选择信号控制的多个上拉/下拉驱动块，每个所述上拉/下拉驱动块包括具有 一个预期的阻抗。

公开(公告)号：US20070182453A1

公开(公告)日：2007-08-09

申请号：US11638454

申请日：2006-12-14

Applicant: Hyung Dong Lee

Inventor： Hyung Dong Lee

IPC: H03K19/094

CPC classification number: H03K19/094

Abstract: A data output circuit of a semiconductor memory apparatus includes a pre-driver generating pull-up and down signals from driving rising and falling data in active periods of rising and falling clocks, respectively, in accordance with a state of an output enable signal. A main driver generates last output data to a common node from the pull-up and down signals. An assistant pre-driver generates an assistant drive signal, which is activated when the rising data disagrees with the falling data, in correspondence with inputs of the rising data, the falling data, the rising clock, the falling clock, and a pipe output control signal. An assistant main driver generates assistant last output data to the common node from the pull-up and down signals in accordance with a state of the assistant drive signal.

Abstract translation: 半导体存储装置的数据输出电路包括预驱动器，分别根据输出使能信号的状态产生上升沿和下降沿的有效周期中的驱动上升和下降数据的上拉和下拉信号。 主驱动器从上拉和下拉信号产生到公共节点的最后输出数据。 辅助预驱动器产生辅助驱动信号，当上升数据与下降数据不一致时，其与上升数据，下降数据，上升时钟，下降时钟和管道输出控制的输入相对应地被激活 信号。 辅助主驱动器根据辅助驱动信号的状态从上拉和下拉信号产生辅助上一个输出数据到公共节点。

公开(公告)号：US20060150044A1

公开(公告)日：2006-07-06

申请号：US11292734

申请日：2005-12-01

Applicant: Hyung-Dong Lee ,  Eun-Jung Jang

Inventor： Hyung-Dong Lee ,  Eun-Jung Jang

IPC: G06F11/00 ,  G01R31/28

CPC classification number: H04L25/4915

Abstract: The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.