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    Semiconductor memory device capable of stably performing entry and exit operations of self refresh mode and the self refresh method thereof
    1.
    发明授权
    Semiconductor memory device capable of stably performing entry and exit operations of self refresh mode and the self refresh method thereof 失效
    能够稳定地执行自刷新模式的进入和退出操作的半导体存储器件及其自刷新方法

    公开(公告)号：US06990032B2

    公开(公告)日：2006-01-24

    申请号：US10814675

    申请日：2004-03-30

    申请人： Eun-Jung Jang

    发明人： Eun-Jung Jang

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40615 ,  G11C2207/2227 ,  G11C2211/4067

    摘要： A semiconductor memory device includes a clock enable signal self refresh buffer for generating a self refresh clock enable signal by receiving the clock enable signal in the self refresh mode, an internal clock signal generating unit for generating an internal clock signal by receiving the external clock signal, a signal synchronization unit for generating an internal clock enable signal by synchronizing the clock enable signal with the internal clock signal, a level detection unit for generating a level detection signal by detecting levels of the internal clock enable signal and the self refresh clock enable signal, a clock self refresh buffer for receiving the external clock signal during a self refresh mode in response to the level detection signal, and a self refresh command generation unit for activating a self refresh command in response to the level detection signal and inactivating the self refresh command in response to the level detection signal and an output signal of the clock self refresh buffer.

    摘要翻译： 半导体存储器件包括时钟使能信号自刷新缓冲器，用于通过在自刷新模式下接收时钟使能信号来产生自刷新时钟使能信号;内部时钟信号产生单元，用于通过接收外部时钟信号产生内部时钟信号 信号同步单元，用于通过使时钟使能信号与内部时钟信号同步来产生内部时钟使能信号;电平检测单元，用于通过检测内部时钟使能信号和自刷新时钟使能信号的电平来产生电平检测信号; ，响应于电平检测信号在自刷新模式期间接收外部时钟信号的时钟自刷新缓冲器，以及响应于电平检测信号激活自刷新命令并且使自刷新失效的自刷新命令产生单元 响应于电平检测信号和c的输出信号 锁自刷新缓冲区。

    Memory device having delay locked loop
    2.
    发明授权
    Memory device having delay locked loop 有权
    具有延迟锁定环的存储器件

    公开(公告)号：US06985401B2

    公开(公告)日：2006-01-10

    申请号：US10857618

    申请日：2004-06-01

    申请人： Eun Jung Jang ,  Hyung Dong Lee

    发明人： Eun Jung Jang ,  Hyung Dong Lee

    IPC分类号： G11C8/00

    CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  H03L7/0814

    摘要： A memory device minimizes the skew between an external clock and a DQS (or DQ) after the locking state by regulating a delay ratio of a replica delay model to compensate errors of process, temperature or voltage change. The memory device comprises: an input clock buffer for buffering an externally inputted external clock to generate an internal clock; a DLL for delaying the internal clock to synchronize a phase of the external clock with that of a DQS; an output clock buffer for buffering an output clock outputted from the DLL; and an output control unit for generating the DQS using a clock outputted from the output clock buffer. Here, the DLL comprises a replica delay model for modeling delay factors of the input clock buffer and other delay factors until the output clock outputted from the delay line is outputted to the outside of a chip, and for regulating a delay ratio in response to a plurality of control signals inputted externally in a test mode.

    摘要翻译： 存储器件通过调节复制延迟模型的延迟比来补偿过程，温度或电压变化的错误，从而最大限度地减小锁定状态之后的外部时钟和DQS（或DQ）之间的偏差。 存储器件包括：输入时钟缓冲器，用于缓冲外部输入的外部时钟以产生内部时钟; 用于延迟内部时钟以使外部时钟的相位与DQS的相位同步的DLL; 输出时钟缓冲器，用于缓冲从DLL输出的输出时钟; 以及输出控制单元，用于使用从输出时钟缓冲器输出的时钟产生DQS。 这里，DLL包括用于建模输入时钟缓冲器的延迟因子和其他延迟因子的复制延迟模型，直到从延迟线输出的输出时钟被输出到芯片的外部，并且用于响应于 在测试模式下从外部输入的多个控制信号。

    DLL with reduced size and semiconductor memory device including DLL and locking operation method of the same
    4.
    发明授权
    DLL with reduced size and semiconductor memory device including DLL and locking operation method of the same 有权
    具有减小的DLL和半导体存储器件的DLL包括DLL和锁定操作方法相同

    公开(公告)号：US07542358B2

    公开(公告)日：2009-06-02

    申请号：US11528563

    申请日：2006-09-28

    申请人： Eun Jung Jang

    发明人： Eun Jung Jang

    IPC分类号： G11C17/00

    CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/222 ,  G11C2207/108

    摘要： A delay locked loop(DLL) includes a phase detector for detecting phase difference between input clock signals and feedback clock signals, and outputting phase detection signals according to results of the detection, a delay line for delaying the input clock signals in response to first and second delay control signals, and outputting delay clock signals, a delay controller for generating the first and the second delay control signals in response to the phase detection signals, and a delay model for delaying reference clock signals during predetermined time, and outputting the delayed signals as the feedback clock signals.

    摘要翻译： 延迟锁定环（DLL）包括用于检测输入时钟信号和反馈时钟信号之间的相位差的相位检测器，并且根据检测结果输出相位检测信号，延迟线，用于响应于第一和 第二延迟控制信号，并输出延迟时钟信号;延迟控制器，用于响应于相位检测信号产生第一和第二延迟控制信号;以及延迟模型，用于在预定时间内延迟基准时钟信号，并输出延迟信号 作为反馈时钟信号。

    Semiconductor memory device capable of stably performing entry and exit operations of self refresh mode and the self refresh method thereof
    5.
    发明申请
    Semiconductor memory device capable of stably performing entry and exit operations of self refresh mode and the self refresh method thereof 失效
    能够稳定地执行自刷新模式的进入和退出操作的半导体存储器件及其自刷新方法

    公开(公告)号：US20050195674A1

    公开(公告)日：2005-09-08

    申请号：US10814675

    申请日：2004-03-30

    申请人： Eun-Jung Jang

    发明人： Eun-Jung Jang

    IPC分类号： G11C11/406 ,  G11C7/00

    CPC分类号： G11C11/40615 ,  G11C2207/2227 ,  G11C2211/4067

    摘要： A semiconductor memory device includes a clock enable signal self refresh buffer for generating a self refresh clock enable signal by receiving the clock enable signal in the self refresh mode, an internal clock signal generating unit for generating an internal clock signal by receiving the external clock signal, a signal synchronization unit for generating an internal clock enable signal by synchronizing the clock enable signal with the internal clock signal, a level detection unit for generating a level detection signal by detecting levels of the internal clock enable signal and the self refresh clock enable signal, a clock self refresh buffer for receiving the external clock signal during a self refresh mode in response to the level detection signal, and a self refresh command generation unit for activating a self refresh command in response to the level detection signal and inactivating the self refresh command in response to the level detection signal and an output signal of the clock self refresh buffer.

    摘要翻译： 半导体存储器件包括时钟使能信号自刷新缓冲器，用于通过在自刷新模式下接收时钟使能信号来产生自刷新时钟使能信号;内部时钟信号产生单元，用于通过接收外部时钟信号产生内部时钟信号 信号同步单元，用于通过使时钟使能信号与内部时钟信号同步来产生内部时钟使能信号;电平检测单元，用于通过检测内部时钟使能信号和自刷新时钟使能信号的电平来产生电平检测信号; ，响应于电平检测信号在自刷新模式期间接收外部时钟信号的时钟自刷新缓冲器，以及响应于电平检测信号激活自刷新命令并且使自刷新失效的自刷新命令产生单元 响应于电平检测信号和c的输出信号 锁自刷新缓冲区。

    On-chip data transmission control apparatus and method
    9.
    发明申请
    On-chip data transmission control apparatus and method 失效

    公开(公告)号：US20060150044A1

    公开(公告)日：2006-07-06

    申请号：US11292734

    申请日：2005-12-01

    申请人： Hyung-Dong Lee ,  Eun-Jung Jang

    发明人： Hyung-Dong Lee ,  Eun-Jung Jang

    IPC分类号： G06F11/00 ,  G01R31/28

    CPC分类号： H04L25/4915

    摘要： The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.

    On-chip data transmission control apparatus and method
    10.
    发明授权
    On-chip data transmission control apparatus and method 失效
    片上数据传输控制装置及方法

    公开(公告)号：US07516382B2

    公开(公告)日：2009-04-07

    申请号：US11292734

    申请日：2005-12-01

    申请人： Hyung-Dong Lee ,  Eun-Jung Jang

    发明人： Hyung-Dong Lee ,  Eun-Jung Jang

    IPC分类号： G01R31/28

    CPC分类号： H04L25/4915

    摘要： The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.

    摘要翻译： 片上数据传输控制器包括数据比较单元，用于将当前数据与先前数据进行比较，并且如果相转移的数据位数大于预设数量则发出反转标志;第一数据反转单元， 反转标志被激活并将反相数据提供到数据总线上的当前数据;以及第二数据反转单元，用于在反转标志被激活时反转经由数据总线发送的数据的相位并输出反相数据。 通过该控制器，通过减少通过GIO线输入的数据的转移次数，可以减少随着待发送的数据数量的增加而大幅度地发生的片上噪声，在使用多步预贴片结构来提高 存储器件的操作速度。