公开(公告)号：US06919745B2

公开(公告)日：2005-07-19

申请号：US10635913

申请日：2003-08-07

申请人： Seong-Hoon Lee ,  Jun-Hong Ahn ,  Joo-Sun Choi

发明人： Seong-Hoon Lee ,  Jun-Hong Ahn ,  Joo-Sun Choi

IPC分类号： G11C11/407 ,  G06F1/10 ,  G11C7/22 ,  G11C8/00 ,  G11C11/4076 ,  H03K5/131 ,  H03K5/135 ,  H03L7/081 ,  H03L7/089 ,  H03L7/06

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/4076 ,  H03K5/133 ,  H03K5/135 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/089

摘要： The present invention related to a ring-resister controlled DLL with fine delay line and a direct skew sensing detector, which is applicable to circuitry for compensating skew between external and internal clocks. The ring-register controlled delay locked loop according to the present invention comprises: a first delay group including a plurality of unit delay elements which are lineally coupled to each other for delaying an input clock signal; a second delay group including a plurality of unit delay elements which are circularly coupled to each other for delaying an output signal from the first delay group; a first control means for determining an amount of lineal delay in the first delay group; and a second control means for determining an amount of circular delay in the first delay group.

摘要翻译： 本发明涉及具有精细延迟线的环形阻抗控制DLL和直接偏斜感测检测器，其可应用于补偿外部和内部时钟之间的偏斜的电路。 根据本发明的环形寄存器控制的延迟锁定环包括：包括多个单元延迟元件的第一延迟组，它们彼此线性耦合以延迟输入时钟信号; 第二延迟组，包括相互循环耦合的多个单位延迟元件，用于延迟来自第一延迟组的输出信号; 第一控制装置，用于确定第一延迟组中的线路延迟量; 以及第二控制装置，用于确定第一延迟组中的循环延迟量。