公开(公告)号：US20120270372A1

公开(公告)日：2012-10-25

申请号：US13528466

申请日：2012-06-20

Applicant: Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

Inventor： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

IPC: H01L21/336

CPC classification number: H01L33/0041 ,  G02F1/134363 ,  G02F1/136209

Abstract: An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

公开(公告)号：US08125603B2

公开(公告)日：2012-02-28

申请号：US12121441

申请日：2008-05-15

Applicant: Jae Young Oh ,  Dong Su Shin ,  Jae Kyun Lee ,  Joon Young Yang ,  Kum Mi Oh

Inventor： Jae Young Oh ,  Dong Su Shin ,  Jae Kyun Lee ,  Joon Young Yang ,  Kum Mi Oh

IPC: G02F1/1343

CPC classification number: G02F1/134363

Abstract: An in-plane switching mode LCD having a plurality of pixels arranged in a matrix includes a gate line formed on a lower substrate, a data line formed such that the data line intersect the gate line to define a pixel region, a TFT (Thin Film Transistor) formed at the intersection of the gate line and the data line, a pixel electrode connected to the TFT, a common electrode to generate a horizontal electric field with the pixel electrode, and a common line supplying common voltage to the common electrode, wherein the common line comprises a first common line formed parallel to the gate line in a lower portion of the pixel region, a second common line formed parallel to the date line in a side portion of the pixel region adjacent to the data line, and a third common line formed parallel to the gate line in a upper portion of the pixel region, and wherein the data line comprises a pair of sub-lines facing directly with each other in every two pixel regions.

Abstract translation: 具有排列成矩阵的多个像素的面内切换模式LCD包括形成在下基板上的栅极线，形成为使得数据线与栅极线相交以限定像素区域的数据线，TFT（薄膜 晶体管），形成在栅极线和数据线的交点处，连接到TFT的像素电极，用于产生与像素电极的水平电场的公共电极以及向公共电极提供公共电压的公共线，其中 公共线包括在像素区域的下部平行于栅极线形成的第一公共线，与邻近数据线的像素区域的侧部中的日期线平行的第二公共线，以及第三公共线 在像素区域的上部平行于栅极线形成的公共线，并且其中数据线包括在每两个像素区域中彼此直接相对的一对子线。

公开(公告)号：US20120008082A1

公开(公告)日：2012-01-12

申请号：US13241069

申请日：2011-09-22

Applicant: Jae Young OH ,  Dong Su Shin ,  Jae Kyun Lee ,  Joon Young Yang ,  Kum Mi Oh

Inventor： Jae Young OH ,  Dong Su Shin ,  Jae Kyun Lee ,  Joon Young Yang ,  Kum Mi Oh

IPC: G02F1/1343

CPC classification number: G02F1/134363

Abstract: An in-plane switching mode LCD having a plurality of pixels arranged in a matrix includes a gate line formed on a lower substrate, a data line formed such that the data line intersect the gate line to define a pixel region, a TFT (Thin Film Transistor) formed at the intersection of the gate line and the data line, a pixel electrode connected to the TFT, a common electrode to generate a horizontal electric field with the pixel electrode, and a common line supplying common voltage to the common electrode, wherein the common line comprises a first common line formed parallel to the gate line, a second common line formed parallel to the date line in a side portion of the pixel region adjacent to the data line, and a third common line formed parallel to the gate line and disposed between a first row and a second row of the matrix.

Abstract translation: 具有排列成矩阵的多个像素的面内切换模式LCD包括形成在下基板上的栅极线，形成为使得数据线与栅极线相交以限定像素区域的数据线，TFT（薄膜 晶体管），形成在栅极线和数据线的交点处，连接到TFT的像素电极，用于产生与像素电极的水平电场的公共电极，以及向公共电极提供公共电压的公共线，其中 公共线包括与栅极线平行形成的第一公共线，与数据线相邻的像素区域的侧部平行于日期线形成的第二公共线，以及平行于栅极线形成的第三公共线 并且设置在矩阵的第一行和第二行之间。

公开(公告)号：US07923784B2

公开(公告)日：2011-04-12

申请号：US12398323

申请日：2009-03-05

Applicant: Kwang Kee Chae ,  Jae Seon Yu ,  Jae Kyun Lee

Inventor： Kwang Kee Chae ,  Jae Seon Yu ,  Jae Kyun Lee

IPC: H01L21/70 ,  H01L27/088 ,  H01L21/336 ,  H01L21/3205

CPC classification number: H01L21/823481 ,  H01L21/823437

Abstract: A semiconductor device includes a semiconductor substrate with an isolation layer formed in the semiconductor substrate to delimit active regions. Recess patterns for gates are defined in the active regions and the isolation layer. Gate patterns are formed in and over the recess patterns for gates, and a gate spacer is formed to cover the gate patterns. The recess patterns for gates have a first depth in the active regions and a second depth, which is greater than the first depth, in the isolation layer. Gaps are created between the gate patterns and upper parts of the recess patterns for gates that are defined in the isolation layer. The gate spacer fills the gaps and protects the gate spacer so as to prevent bridging.

Abstract translation: 半导体器件包括半导体衬底，其具有形成在半导体衬底中以限定有源区的隔离层。 在活动区域​​和隔离层中限定栅极的凹槽图案。 栅极图案形成在用于栅极的凹槽图案中和上方，并且形成栅极间隔物以覆盖栅极图案。 栅极的凹槽图案在有源区域中具有第一深度，并且在隔离层中具有大于第一深度的第二深度。 在隔离层中限定的门的凹槽图案的栅极图案和上部之间产生间隙。 栅极间隔物填充间隙并保护栅极间隔物以防止桥接。

公开(公告)号：US20090130841A1

公开(公告)日：2009-05-21

申请号：US12163434

申请日：2008-06-27

Applicant: Yong-Tae CHO ,  Jae-Kyun LEE ,  Sang- Rok OH

Inventor： Yong-Tae CHO ,  Jae-Kyun LEE ,  Sang- Rok OH

IPC: H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L21/76844

Abstract: A method for forming a contact in a semiconductor device, comprises providing a substrate, forming a plurality of conductive patterns and a passivation layer surrounding the conductive patterns over the substrate, forming an insulation layer covering the conductive patterns and passivation layer, forming a mask pattern for a contact over the insulation layer, forming a first opening by performing an isotropic etch process on the insulation layer using the mask pattern as an etch mask, wherein the isotropic etch process is performed until the insulation layer meets the passivation layer, forming a barrier layer over a resultant structure of the first opening, exposing the insulation layer by performing an anisotropic etch process using the mask pattern as an etch mask, and forming a second opening exposing the substrate by performing a self aligned contact (SAC) process using the mask pattern and barrier layer as an etch mask.

Abstract translation: 一种用于在半导体器件中形成接触的方法，包括提供衬底，在衬底上形成多个导电图案和围绕导电图案的钝化层，形成覆盖导电图案和钝化层的绝缘层，形成掩模图案 对于绝缘层上的接触，通过使用掩模图案作为蚀刻掩模对绝缘层进行各向同性蚀刻工艺形成第一开口，其中执行各向同性蚀刻工艺，直到绝缘层与钝化层相交，形成屏障 在所述第一开口的结果结构上方，通过使用所述掩模图案作为蚀刻掩模执行各向异性蚀刻工艺来暴露所述绝缘层，以及通过使用所述掩模通过执行自对准接触（SAC）工艺来形成第二开口，所述第二开口暴露所述衬底 图案和阻挡层作为蚀刻掩模。

公开(公告)号：US07525622B2

公开(公告)日：2009-04-28

申请号：US11475037

申请日：2006-06-27

Applicant: Myoung Su Yang ,  Jae Kyun Lee

Inventor： Myoung Su Yang ,  Jae Kyun Lee

IPC: G02F1/1337

CPC classification number: G02F1/13394

Abstract: A liquid crystal display device includes a first substrate and a second substrate facing each other; a gate line and a data line crossing each other to define a pixel region on the first substrate; a thin film transistor on the first substrate and adjacent to the pixel region; a column spacer located on the second substrate; a protrusion located on the first substrate at a location corresponding to the protrusion, the protrusion having a hollow portion and a surrounding wall surrounding the hollow portion, the hollow portion being exposed at the top side of the protrusion; and a liquid crystal layer interposed between the first substrate and the second substrate.

Abstract translation: 液晶显示装置包括第一基板和彼此面对的第二基板; 栅极线和数据线彼此交叉以限定第一衬底上的像素区域; 在所述第一基板上并且邻近所述像素区域的薄膜晶体管; 位于所述第二基板上的柱间隔物; 位于与所述突起相对应的位置处的所述第一基板上的突起，所述突起具有中空部分和围绕所述中空部分的围绕壁，所述中空部分在所述突起的顶侧露出; 以及插入在第一基板和第二基板之间的液晶层。

公开(公告)号：US20090040166A1

公开(公告)日：2009-02-12

申请号：US12222436

申请日：2008-08-08

Applicant: Jae Kyun Lee ,  Kum Mi Oh ,  Jae Young Oh ,  Dong Su Shin

Inventor： Jae Kyun Lee ,  Kum Mi Oh ,  Jae Young Oh ,  Dong Su Shin

IPC: G09G3/36

CPC classification number: G02F1/1345 ,  G02F1/13458 ,  G02F1/136286 ,  G02F2201/121

Abstract: A liquid crystal display device includes a display panel including a display area and a non-display area surrounding the display area, a plurality of gate lines and data lines arranged on the display area to intersect each other, so as to define a plurality of pixel regions, a plurality of thin-film transistors formed at respective intersections of the gate lines and the data lines, a plurality of pixel electrodes formed on the respective pixel regions and connected to the thin film transistors, and at least one first common line provided between the data lines and arranged parallel to the data lines.

Abstract translation: 一种液晶显示装置，包括显示面板和显示区域周围的非显示区域的显示面板，布置在显示区域上的多条栅极线和数据线，以形成多个像素 形成在栅极线与数据线的各交叉处的多个薄膜晶体管，形成在各个像素区域并连接到薄膜晶体管的多个像素电极，以及至少一个第一公共线， 数据线并排布置在数据线上。

公开(公告)号：US20080166829A1

公开(公告)日：2008-07-10

申请号：US12007212

申请日：2008-01-08

Applicant: Goe-Sung Chae ,  Jae-Kyun Lee ,  Yong-Sup Hwang

Inventor： Goe-Sung Chae ,  Jae-Kyun Lee ,  Yong-Sup Hwang

IPC: H01L21/70

CPC classification number: G02F1/13458 ,  G02F1/1362 ,  G02F1/136213

Abstract: According to an embodiment, a fabrication method includes forming a gate line disposed along a first direction and a common line parallel to the gate line on a substrate, the gate and common lines spaced apart from each other, forming a gate insulating layer on the gate and common lines, forming a semiconductor layer on the gate insulating layer, forming a source electrode and a pixel electrode of transparent conductive material, the pixel electrode including a drain electrode portion, the drain electrode portion overlapping the semiconductor layer, forming a passivation layer including a first contact hole and an open portion, the first contact hole exposing the source electrode and the open portion exposing the pixel electrode, respectively, and forming a data line disposed along a second direction on the passivation layer, the data line connected to the source electrode through the first contact hole and crossing the gate line.

Abstract translation: 根据实施例，制造方法包括：形成沿着第一方向设置的栅极线和与基板上的栅极线平行的公共线，栅极和公共线彼此间隔开，在栅极上形成栅极绝缘层 和公共线，在栅极绝缘层上形成半导体层，形成透明导电材料的源电极和像素电极，所述像素电极包括漏电极部分，所述漏电极部分与所述半导体层重叠，形成钝化层，所述钝化层包括 第一接触孔和开口部分，所述第一接触孔分别暴露所述源极电极和所述开放部分，暴露所述像素电极，并且形成沿所述钝化层沿着第二方向布置的数据线，所述数据线连接到所述源极 电极通过第一接触孔并与栅极线交叉。

公开(公告)号：US20080160718A1

公开(公告)日：2008-07-03

申请号：US12004240

申请日：2007-12-18

Applicant: Hae-Jung Lee ,  Hyun-Sik Park ,  Jae-Kyun Lee

Inventor： Hae-Jung Lee ,  Hyun-Sik Park ,  Jae-Kyun Lee

IPC: H01L21/762

CPC classification number: H01L21/76232

Abstract: A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.

Abstract translation: 在半导体器件中制造隔离层的方法包括：提供衬底，在衬底上形成沟槽，沿着沟槽的表面形成衬里氮化物层和衬垫氧化物层，形成具有不同蚀刻选择比的绝缘层 与衬垫氧化物层上的衬垫氧化物层的衬垫氧化物层的形成自旋在电介质（SOD）氧化物层上形成，以填充绝缘层上的一部分沟槽，并形成高密度等离子体（HDP）氧化物层，用于填充剩余的 一部分沟槽。

公开(公告)号：US06906342B1

公开(公告)日：2005-06-14

申请号：US09466961

申请日：1999-12-20

Applicant: Youn Gyoung Chang ,  Jeong Hyun Kim ,  Jae Kyun Lee

Inventor： Youn Gyoung Chang ,  Jeong Hyun Kim ,  Jae Kyun Lee

IPC: H01L29/786 ,  H01L27/12 ,  H01L27/146 ,  H01L29/417 ,  H01L29/45 ,  H01L29/04

CPC classification number: H01L27/14601 ,  H01L27/12 ,  H01L27/14643 ,  H01L29/41733 ,  H01L29/458

Abstract: An optical detecting sensor includes a sensor thin film transistor generating an optical current in response to incident light reflected from an object; a storage capacitor storing charges of the optical current generated in the sensor thin film transistor; and a switch thin film transistor controlling release of the stored charges of the storage capacitor to an outer circuit for display of image of the object, having dual-layered source and drain electrodes of transparent conducting material and metal material, an active layer and a gate electrode. The switch thin film transistor further includes an ohmic contact layer on the active layer through which the dual-layered drain and source electrodes contact the active layer.

Abstract translation: 光检测传感器包括响应于从物体反射的入射光而产生光电流的传感器薄膜晶体管; 存储电容器，其存储在所述传感器薄膜晶体管中产生的光电流的电荷; 以及开关薄膜晶体管，其控制存储电容器的存储电荷释放到用于显示对象的图像的外部电路，具有透明导电材料和金属材料的双层源极和漏极，活性层和栅极 电极。 开关薄膜晶体管还包括有源层上的欧姆接触层，双层漏极和源电极通过该接触层与有源层接触。