公开(公告)号：US08345175B2

公开(公告)日：2013-01-01

申请号：US13528466

申请日：2012-06-20

申请人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

发明人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

IPC分类号： G02F1/1343

CPC分类号： H01L33/0041 ,  G02F1/134363 ,  G02F1/136209

摘要： An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

公开(公告)号：US20120270372A1

公开(公告)日：2012-10-25

申请号：US13528466

申请日：2012-06-20

申请人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

发明人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

IPC分类号： H01L21/336

CPC分类号： H01L33/0041 ,  G02F1/134363 ,  G02F1/136209

摘要： An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

公开(公告)号：US20120008072A1

公开(公告)日：2012-01-12

申请号：US13238987

申请日：2011-09-21

申请人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

发明人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

IPC分类号： G02F1/1335 ,  H01L33/08 ,  G02F1/1343

CPC分类号： H01L33/0041 ,  G02F1/134363 ,  G02F1/136209

摘要： An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

摘要翻译： 面内切换模式液晶显示装置的阵列基板包括基板，沿基板的第一方向设置的栅极线，沿着第二方向设置并与栅极线交叉以限定像素区域的数据线， 连接到栅极线和数据线的薄膜晶体管，设置在像素区域中并连接到薄膜晶体管的像素电极，设置在像素区域中并与像素电极交替的公共电极，位于数据线下面的半导体层，以及 包括宽度大于数据线的宽度的部分，以及包括不透明材料并设置在半导体层下方的第一阻挡图案。

公开(公告)号：US08223281B2

公开(公告)日：2012-07-17

申请号：US13238987

申请日：2011-09-21

申请人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

发明人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

IPC分类号： G02F1/1343

CPC分类号： H01L33/0041 ,  G02F1/134363 ,  G02F1/136209

摘要： An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

摘要翻译： 面内切换模式液晶显示装置的阵列基板包括基板，沿基板的第一方向设置的栅极线，沿着第二方向设置并与栅极线交叉以限定像素区域的数据线， 连接到栅极线和数据线的薄膜晶体管，设置在像素区域中并连接到薄膜晶体管的像素电极，设置在像素区域中并与像素电极交替的公共电极，位于数据线下面的半导体层，以及 包括宽度大于数据线的宽度的部分，以及包括不透明材料并设置在半导体层下方的第一阻挡图案。

公开(公告)号：US08040445B2

公开(公告)日：2011-10-18

申请号：US11639902

申请日：2006-12-15

申请人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

发明人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

IPC分类号： G02F1/1343

CPC分类号： H01L33/0041 ,  G02F1/134363 ,  G02F1/136209

摘要： An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

摘要翻译： 面内切换模式液晶显示装置的阵列基板包括基板，沿基板的第一方向设置的栅极线，沿着第二方向设置并与栅极线交叉以限定像素区域的数据线， 连接到栅极线和数据线的薄膜晶体管，设置在像素区域中并连接到薄膜晶体管的像素电极，设置在像素区域中并与像素电极交替的公共电极，位于数据线下面的半导体层，以及 包括宽度大于数据线的宽度的部分，以及包括不透明材料并设置在半导体层下方的第一阻挡图案。

公开(公告)号：US20070242203A1

公开(公告)日：2007-10-18

申请号：US11639902

申请日：2006-12-15

申请人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

发明人： Jung-Eun Lee ,  Jae-Kyun Lee ,  Moo-Hyoung Song ,  Seung-Chan Choi

IPC分类号： G02F1/1343

CPC分类号： H01L33/0041 ,  G02F1/134363 ,  G02F1/136209

摘要： An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer.

摘要翻译： 面内切换模式液晶显示装置的阵列基板包括基板，沿基板的第一方向设置的栅极线，沿着第二方向设置并与栅极线交叉以限定像素区域的数据线， 连接到栅极线和数据线的薄膜晶体管，设置在像素区域中并连接到薄膜晶体管的像素电极，设置在像素区域中并与像素电极交替的公共电极，位于数据线下面的半导体层，以及 包括宽度大于数据线的宽度的部分，以及包括不透明材料并设置在半导体层下方的第一阻挡图案。

公开(公告)号：US20080166829A1

公开(公告)日：2008-07-10

申请号：US12007212

申请日：2008-01-08

申请人： Goe-Sung Chae ,  Jae-Kyun Lee ,  Yong-Sup Hwang

发明人： Goe-Sung Chae ,  Jae-Kyun Lee ,  Yong-Sup Hwang

IPC分类号： H01L21/70

CPC分类号： G02F1/13458 ,  G02F1/1362 ,  G02F1/136213

摘要： According to an embodiment, a fabrication method includes forming a gate line disposed along a first direction and a common line parallel to the gate line on a substrate, the gate and common lines spaced apart from each other, forming a gate insulating layer on the gate and common lines, forming a semiconductor layer on the gate insulating layer, forming a source electrode and a pixel electrode of transparent conductive material, the pixel electrode including a drain electrode portion, the drain electrode portion overlapping the semiconductor layer, forming a passivation layer including a first contact hole and an open portion, the first contact hole exposing the source electrode and the open portion exposing the pixel electrode, respectively, and forming a data line disposed along a second direction on the passivation layer, the data line connected to the source electrode through the first contact hole and crossing the gate line.

摘要翻译： 根据实施例，制造方法包括：形成沿着第一方向设置的栅极线和与基板上的栅极线平行的公共线，栅极和公共线彼此间隔开，在栅极上形成栅极绝缘层 和公共线，在栅极绝缘层上形成半导体层，形成透明导电材料的源电极和像素电极，所述像素电极包括漏电极部分，所述漏电极部分与所述半导体层重叠，形成钝化层，所述钝化层包括 第一接触孔和开口部分，所述第一接触孔分别暴露所述源极电极和所述开放部分，暴露所述像素电极，并且形成沿所述钝化层沿着第二方向布置的数据线，所述数据线连接到所述源极 电极通过第一接触孔并与栅极线交叉。

公开(公告)号：US20080160718A1

公开(公告)日：2008-07-03

申请号：US12004240

申请日：2007-12-18

申请人： Hae-Jung Lee ,  Hyun-Sik Park ,  Jae-Kyun Lee

发明人： Hae-Jung Lee ,  Hyun-Sik Park ,  Jae-Kyun Lee

IPC分类号： H01L21/762

CPC分类号： H01L21/76232

摘要： A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.

摘要翻译： 在半导体器件中制造隔离层的方法包括：提供衬底，在衬底上形成沟槽，沿着沟槽的表面形成衬里氮化物层和衬垫氧化物层，形成具有不同蚀刻选择比的绝缘层 与衬垫氧化物层上的衬垫氧化物层的衬垫氧化物层的形成自旋在电介质（SOD）氧化物层上形成，以填充绝缘层上的一部分沟槽，并形成高密度等离子体（HDP）氧化物层，用于填充剩余的 一部分沟槽。

公开(公告)号：US6107640A

公开(公告)日：2000-08-22

申请号：US832692

申请日：1997-04-11

申请人： Jae-Yong Park ,  Jae-Kyun Lee ,  Jung-Hoan Kim

发明人： Jae-Yong Park ,  Jae-Kyun Lee ,  Jung-Hoan Kim

IPC分类号： B60R21/00 ,  H01L21/31 ,  H01L21/336 ,  H01L29/786 ,  H01L29/04 ,  H01L27/01

CPC分类号： H01L29/66765 ,  H01L29/78618

摘要： A semiconductor device for a TFT includes a first semiconductor layer to be used as a channel, which is formed on a portion of an insulating layer in correspondence with an underlying gate electrode. The semiconductor device further includes a second semiconductor layer, an ohmic contact layer, and a metal layer formed on the insulating layer and the first semiconductor layer and patterned to expose portions of the insulating layer and the first semiconductor layer. The patterned metal layer forms source and drain electrodes. The semiconductor device also includes a passivation layer, which covers the insulating layer, the first semiconductor layer and the source and drain electrodes, and a pixel electrode, which contacts the drain electrode though a contact hole in the passivation layer.

摘要翻译： 用于TFT的半导体器件包括用作沟道的第一半导体层，其形成在与下面的栅电极对应的绝缘层的一部分上。 半导体器件还包括形成在绝缘层和第一半导体层上的第二半导体层，欧姆接触层和金属层，并被图案化以暴露绝缘层和第一半导体层的部分。 图案化金属层形成源极和漏极。 半导体器件还包括覆盖绝缘层，第一半导体层和源极和漏极的钝化层和通过钝化层中的接触孔接触漏电极的像素电极。

公开(公告)号：US5990998A

公开(公告)日：1999-11-23

申请号：US829121

申请日：1997-04-10

申请人： Jae-Yong Park ,  Jae-Kyun Lee ,  Jung-Hoan Kim ,  Ki-Hyun Lyu ,  Kyu-Hyun Lee

发明人： Jae-Yong Park ,  Jae-Kyun Lee ,  Jung-Hoan Kim ,  Ki-Hyun Lyu ,  Kyu-Hyun Lee

IPC分类号： G02F1/133 ,  G02F1/1362 ,  G02F1/136 ,  G02F1/1343

CPC分类号： G02F1/136213 ,  G02F1/136286

摘要： A method of manufacturing an active matrix LCD is disclosed whereby gate bus lines, gate electrodes and source bus line segments are patterned from the same vacuum deposited first metal layer. An insulating layer, semiconductor layer, extrinsic semiconductor layer and second metal layer are then successively deposited on the substrate. A TFT channel region is formed by etching each of these layers in a second patterning process. During this step, storage capacitors may be formed by patterning the second metal layer so that it overlaps part of the gate bus lines. A transparent conductive layer is next deposited on the substrate. Pixel electrodes are then formed by patterning the transparent conductive layer in a third patterning process. Further, using a portion of the transparent conductive layer as a mask, the second metal layer and part of the extrinsic semiconductor layer are etched to form source and drain electrodes. Additionally, the transparent conductive layer can be patterned to provide an electrical connection between adjacent bus line segments to form a plurality of electrically continuous source bus lines.

摘要翻译： 公开了一种制造有源矩阵LCD的方法，其中栅极总线，栅电极和源极总线段被从相同的真空沉积的第一金属层图案化。 然后将绝缘层，半导体层，非本征半导体层和第二金属层依次沉积在基板上。 通过在第二图案化工艺中蚀刻这些层中的每一层来形成TFT沟道区。 在该步骤期间，可以通过对第二金属层进行图案化以使其与栅极总线的一部分重叠而形成存储电容器。 接着在衬底上沉积透明导电层。 然后通过在第三图案化工艺中图案化透明导电层来形成像素电极。 此外，使用透明导电层的一部分作为掩模，蚀刻第二金属层和非本征半导体层的一部分以形成源极和漏极。 另外，透明导电层可被图案化以在相邻的总线段之间提供电连接，以形成多个电连续的源极总线。