公开(公告)号：US07177970B2

公开(公告)日：2007-02-13

申请号：US10274881

申请日：2002-10-22

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/14 ,  G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

摘要翻译： 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US20060117142A1

公开(公告)日：2006-06-01

申请号：US11331083

申请日：2006-01-13

申请人： Seiji Kaneko ,  Hiroki Kanai

发明人： Seiji Kaneko ,  Hiroki Kanai

IPC分类号： G06F12/00

CPC分类号： G06F12/0866 ,  G06F3/0611 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0689 ,  G06F12/0815 ,  G06F12/0817 ,  Y10S707/99952

摘要： A disk array device is equipped with a plurality of input/output channels that receive data input/output requests from an external device, a plurality of cache memories provided for the corresponding respective input/output channels, each of the cache memories connected to each of the corresponding respective input/output channels, a disk drive device, a disk control module that performs data input/output to and from the disk drive device, and a communication module that communicatively connects the input/output channels with the disk control module. The disk array device also includes a consistency maintaining module that can perform a consistency maintaining processing to maintain consistency of data stored in each of the cache memories. According to the content of the data input/output request received from the external device, an execution order of a response processing to respond to the external device according to the data input/output request and the consistency maintaining processing is controlled.

公开(公告)号：US07047388B2

公开(公告)日：2006-05-16

申请号：US10656493

申请日：2003-09-05

申请人： Seiji Kaneko

发明人： Seiji Kaneko

IPC分类号： G06F12/00

CPC分类号： G06F3/0661 ,  G06F3/0607 ,  G06F3/0689

摘要： The present invention provides a control method for a storage device controller system provided with a first storage device controller that is connected to first and second storage devices storing data in the CKD format and the FBA format, respectively, and that has first and second communications control means that receive data input/output requests from a mainframe computer and an open system computer, respectively, and a second storage device that is connected to a third storage device storing data in the CKD format and that has third communications means connected to the second communications means, wherein the first storage device controller transmits a command to the second storage device controller if a data read request received from the open system computer is for data stored on the third storage device, and transmits the data that are read out from the third storage device by the second storage device controller to the open system computer.

公开(公告)号：US06341323B2

公开(公告)日：2002-01-22

申请号：US09777960

申请日：2001-02-07

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F1300

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

摘要翻译： 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US06219735B1

公开(公告)日：2001-04-17

申请号：US09477666

申请日：2000-01-05

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Hideaki Gemma ,  Tetsuhiko Okada ,  Kazuhiko Komori ,  Koichi Okazawa

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Hideaki Gemma ,  Tetsuhiko Okada ,  Kazuhiko Komori ,  Koichi Okazawa

IPC分类号： G06F1312

CPC分类号： G06F13/364

摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

摘要翻译： 一种信息处理系统，其中作为执行对模块的读取访问以作为从机操作的主机的模块请求总线仲裁器以提供具有总线主控请求信号的母线的掌握，并且它同时断言最后一个周期 信号，以通知总线仲裁器下一个周期将是主机使用的最后一个周期的事实。 随后，当主机已经使用由总线仲裁器通过总线使用授权信号授予的总线时，它通过在下一个周期中使用总线将地址传送到从机，从而开始读取访问。 读取权限后，主人释放总线主控权。 只有当从站未能接受传送的地址时，它会在地址的传输周期不被接受的两个周期之后重新生成重试请求信号。 在这种情况下，在断言信号的周期之前执行传送两个周期的模块再次执行之前执行的传送。 因此，要传输的地址只能在一个周期内传输到模块准备好接受地址。

公开(公告)号：US5377341A

公开(公告)日：1994-12-27

申请号：US710336

申请日：1991-06-05

申请人： Seiji Kaneko ,  Toshiyuki Kinoshita ,  Akio Yamamoto ,  Yasuhisa Tamura

发明人： Seiji Kaneko ,  Toshiyuki Kinoshita ,  Akio Yamamoto ,  Yasuhisa Tamura

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F15/16 ,  G06F15/177 ,  G06F12/02

CPC分类号： G06F12/0855

摘要： In buffer storage equipment, storage control is carried out by a pipeline having two stages including a stage for executing out-of-order processing for processing a succeeding request with priority and a stage for not executing out-of-order processing. By this storage control, a request processing order is guaranteed at the stage for not executing out-of-order processing and a request is caused to wait at the stage for executing out-of-order processing.

摘要翻译： 在缓冲存储设备中，通过具有两级的流水线进行存储控制，该流水线包括用于执行优先处理后续请求的无序处理的级和不执行无序处理的级。 通过该存储控制，在阶段保证不执行无序处理的请求处理顺序，并且使请求在用于执行无序处理的阶段等待。

公开(公告)号：US5333289A

公开(公告)日：1994-07-26

申请号：US703458

申请日：1991-05-21

申请人： Seiji Kaneko ,  Masaya Watanabe ,  Toshiyuki Kinoshita ,  Yasuhisa Tamura ,  Masaichiro Yoshioka

发明人： Seiji Kaneko ,  Masaya Watanabe ,  Toshiyuki Kinoshita ,  Yasuhisa Tamura ,  Masaichiro Yoshioka

IPC分类号： G06F11/00 ,  G06F12/06 ,  G11C29/00 ,  G06F12/00

CPC分类号： G06F11/1666 ,  G06F12/0607 ,  G06F11/20 ,  G06F2201/85 ,  G11C29/88

摘要： In a computer system having a main storage equipment comprising a plurality of storage equipments, the storage area of each storage equipment is divided in fixed units and an interleave mode is set for each of fixed nuts. When configuration of the main storage equipment is to be changed by disconnection or coupling of storage equipments, necessary data are moved and the interleave mode is changed for all data of the above described fixed unit.

摘要翻译： 在具有包括多个存储设备的主存储设备的计算机系统中，每个存储设备的存储区域以固定单元划分，并且为每个固定螺母设置交错模式。 当通过存储设备的断开或耦合来改变主存储设备的配置时，移动所需的数据，并且对于上述固定单元的所有数据改变交错模式。