Abstract:
A network switch configured for switching data packets across multiple ports uses decision making logic to generate frame forwarding information. The decision making logic employs a pipelined architecture that enables multiple data frames to be processed simultaneously to increase data throughput. The decision making logic also pipelines access to an address lookup table that stores the data forwarding information. An arbitration circuit provides the decision making device with automatic access to the address table in alternate time slots and also enables other circuits to access the address table in predetermined time slots.
Abstract:
A novel method of enabling a port of a network switch to support connections with multiple VLANs. The method comprises storing VLAN data indicating a plurality of VLAN identifiers corresponding to the multiple VLANs supported by the port. A VLAN identifier of a data packet received via the port is compared with the plurality of VLAN identifiers determined using the stored VLAN data. The data packet is forwarded for further processing if the VLAN identifier matches one of the plurality of VLAN identifiers. However, the data packet is discarded if the VLAN identifier does not match one of the plurality of VLAN identifiers. Moreover, VLAN information corresponding to a VLAN identifier of a data packet to be transmitted from the port is compared with the stored VLAN data to determine whether the VLAN identifier matches one of the plurality of VLAN identifiers supported by the port. The data packet is prevented from being transmitted from the port if the VLAN identifier does not match one of the plurality of VLAN identifiers.
Abstract:
Multiple network switch modules have memory interfaces configured for transferring packet data to respective buffer memories. The memory interfaces are also configured for transfer among each other data units of data frames received from different network switch modules. A shared switching logic monitors (“snoops”) the data units as they are transferred between network switch modules, providing a centralized switching decision logic for multiple network switch modules. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by concurrently executing a prescribed number of successive memory writes or memory reads. A preferred embodiment includes a distributed memory interface in between the network switch modules and a shared memory system.
Abstract:
An integrated multiport switch operating in a packet switched network provides the capability to alter VLAN tags on a port by port basis. An internal rules checker (IRC) analyzes the header of a data frame to determine the frame type: untagged, VLAN-tagged, or priority-tagged. The IRC searches the untagged set table for the set of ports that are untagged for a particular VLAN. The IRC passes a forwarding descriptor that includes the frame type and a operational code (opcode) to a Port Vector FIFO logic (PVF). The PVF is responsible for creating a new opcode that instructs a dequeuing logic to add, remove, modify the VLAN tag, or send the frame unmodified. The opcodes generated by the PVF are individualized for each output port.
Abstract:
A network switch configured for switching data packets across multiple ports uses an address table to generate frame forwarding information. The address table includes aging information used by an internal decision making engine so that aged entries are invalidated after a programmable period of time. The network switch includes a test mode so that the aging function is able to be quickly tested by an external test device.
Abstract:
A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol dynamically allocates external memory bandwidth slots between high data rate ports. An external memory interface determines if a high data rate port makes a request for a bandwidth slot and grants the request if made. The slot is taken from a selected group which is a subset of the total number of slots. If a request for the slot is not made, the external memory interface assigns the slot to another high data rate port. Lower data rate ports in the network switch are assigned fixed slots from those slots not from within the selected group of slots. The dynamic allocation of bandwidth slots between the high data rate port enables the efficient use of limited memory bandwidth resources.
Abstract:
A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to IEEE 802.3 protocol dynamically allocates bandwidth between the switch ports based upon detected activity from the network nodes. The network switch generates an assigned bandwidth value for each active switch port based upon the switch capacity and the number of active switch ports. Each active switch port forwards the assigned bandwidth value to the corresponding network node as an IEEE 802.3x[2] compliant media access control (MAC) control frame, enabling the corresponding network node to calculate its programmed interpacket gap interval following a packet transmission based upon the size of the transmitted packet and the assigned bandwidth. Each active switch port also calculates the programmed interpacket gap to determine if reception of another data packet has begun by the end of the programmed interpacket gap interval. If no data packet is received by the corresponding port after the programmed interpacket gap interval, the network switch considers that switch port as non-active, recalculates, and reassigns the unused bandwidth to the remaining active ports. The dynamic bandwidth allocation by the network switch enables the input buffer size to be optimized without requiring an excessive switch bandwidth.