公开(公告)号：US20220123123A1

公开(公告)日：2022-04-21

申请号：US17498098

申请日：2021-10-11

Applicant: Applied Materials, Inc.

Inventor： Myungsun Kim ,  Andy Lo ,  Eric Davey ,  Michael Stolfi ,  Benjamin Colombeau

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/66

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise an oxide layer and a semiconductor material layer between source regions and drain regions of the device. The method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer. An alternative method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by a surface treatment, and then radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer.

公开(公告)号：US20220059698A1

公开(公告)日：2022-02-24

申请号：US17000546

申请日：2020-08-24

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Mehdi Saremi ,  El Mehdi Bazizi ,  Benjamin Colombeau

IPC: H01L29/78

Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

公开(公告)号：US20210398814A1

公开(公告)日：2021-12-23

申请号：US17348081

申请日：2021-06-15

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Abhishek Dube ,  Sheng-Chin Kung ,  Patricia M. Liu ,  Malcolm J. Bevan ,  Johanes F. Swenberg

IPC: H01L21/28 ,  H01L21/02

Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

公开(公告)号：US20210134986A1

公开(公告)日：2021-05-06

申请号：US17080519

申请日：2020-10-26

Applicant: Applied Materials, Inc.

Inventor： Steven C. Hung ,  Benjamin Colombeau ,  Abhishek Dube ,  Sheng-Chin Kung ,  Patricia M. Liu ,  Malcolm J. Bevan ,  Johanes Swenberg

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/786

Abstract: Processing methods may be performed to produce semiconductor structures that may include a high-k dielectric material. The methods may include forming a silicon layer over a semiconductor substrate. The semiconductor substrate may include silicon germanium. The methods may include oxidizing a portion of the silicon layer to form a sacrificial oxide while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The methods may include removing the sacrificial oxide. The methods may include oxidizing the portion of the silicon layer in contact with the semiconductor substrate to form an oxygen-containing material. The methods may include forming a high-k dielectric material overlying the oxygen-containing material.

公开(公告)号：US10483355B2

公开(公告)日：2019-11-19

申请号：US15792449

申请日：2017-10-24

Applicant: Applied Materials, Inc.

Inventor： Matthias Bauer ,  Hans-Joachim L. Gossmann ,  Benjamin Colombeau

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/26 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L29/165 ,  H01L29/167

Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.