公开(公告)号：US12183798B2

公开(公告)日：2024-12-31

申请号：US17528863

申请日：2021-11-17

Applicant: Applied Materials, Inc.

Inventor： Steven C. H. Hung ,  Benjamin Colombeau ,  Myungsun Kim ,  Srinivas Gandikota ,  Yixiong Yang ,  Jacqueline Samantha Wrench ,  Yong Yang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

Abstract: A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.

公开(公告)号：US20220005937A1

公开(公告)日：2022-01-06

申请号：US17354251

申请日：2021-06-22

Applicant: Applied Materials, Inc.

Inventor： Michael Stolfi ,  Myungsun Kim ,  Benjamin Colombeau ,  Sanjay Natarajan

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US11508828B2

公开(公告)日：2022-11-22

申请号：US17354251

申请日：2021-06-22

Applicant: Applied Materials, Inc.

Inventor： Michael Stolfi ,  Myungsun Kim ,  Benjamin Colombeau ,  Sanjay Natarajan

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US20220037147A1

公开(公告)日：2022-02-03

申请号：US17386724

申请日：2021-07-28

Applicant: Applied Materials, Inc.

Inventor： Myungsun Kim ,  Jingmei Liang ,  Martin J. Seamons ,  Michael Stolfi ,  Benjamin Colombeau

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L27/12

Abstract: Provided are methods of depositing a film in high aspect ratio (AR) structures with small dimensions. The method provides flowable deposition for seamless gap-fill, film densification by low temperature inductively coupled plasma (ICP) treatment (

公开(公告)号：US12062708B2

公开(公告)日：2024-08-13

申请号：US17968068

申请日：2022-10-18

Applicant: Applied Materials, Inc.

Inventor： Michael Stolfi ,  Myungsun Kim ,  Benjamin Colombeau ,  Sanjay Natarajan

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66439 ,  H01L29/0673 ,  H01L29/42392 ,  H01L27/088

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US10177227B1

公开(公告)日：2019-01-08

申请号：US15687747

申请日：2017-08-28

Applicant: Applied Materials, Inc.

Inventor： Naomi Yoshida ,  Lin Dong ,  Shiyu Sun ,  Myungsun Kim ,  Nam Sung Kim ,  Dimitri Kioussis ,  Mikhail Korolik ,  Gaetano Santoro ,  Vanessa Pena

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: The present disclosure provides methods for forming horizontal gate-all-around (hGAA) structure devices. In one example, a method includes selectively and laterally etching a first group of sidewalls of a first layer in a multi-material layer, wherein the multi-material layer comprises repeating pairs of the first layer and a second layer, the first and the second layers having the first group and a second group of sidewalls respectively, the first group of sidewalls from the first layer exposed through openings defined in the multi-material layer and a group of inner spacers formed atop of the second group of sidewalls from the second layer, forming a recess from the first group of sidewalls of the first layer and defining a vertical wall inward from an outer vertical surface of the inner spacer formed atop of the second layers, and forming an epi-silicon layer from the recess of the first layer.

公开(公告)号：US20230039074A1

公开(公告)日：2023-02-09

申请号：US17968068

申请日：2022-10-18

Applicant: Applied Materials, Inc.

Inventor： Michael Stolfi ,  Myungsun Kim ,  Benjamin Colombeau ,  Sanjay Natarajan

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US20220246742A1

公开(公告)日：2022-08-04

申请号：US17583355

申请日：2022-01-25

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  El Mehdi Bazizi ,  Benjamin Colombeau ,  Myungsun Kim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/15

Abstract: Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices comprise a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.

公开(公告)号：US20220123123A1

公开(公告)日：2022-04-21

申请号：US17498098

申请日：2021-10-11

Applicant: Applied Materials, Inc.

Inventor： Myungsun Kim ,  Andy Lo ,  Eric Davey ,  Michael Stolfi ,  Benjamin Colombeau

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/66

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise an oxide layer and a semiconductor material layer between source regions and drain regions of the device. The method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer. An alternative method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by a surface treatment, and then radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer.

公开(公告)号：US20230040606A1

公开(公告)日：2023-02-09

申请号：US17879088

申请日：2022-08-02

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Saurabh Chopra ,  Myungsun Kim ,  Balasubramanian Pranatharthiharan

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.