公开(公告)号：US20050013155A1

公开(公告)日：2005-01-20

申请号：US10621737

申请日：2003-07-17

申请人： Andrey Nikitin ,  Alexander Andreev

发明人： Andrey Nikitin ,  Alexander Andreev

IPC分类号： G06F17/50 ,  G11C11/22

CPC分类号： G06F17/5022

摘要： The present invention is directed to a method and apparatus of IC implementation based on a C++ language description. In an exemplary aspect of the present invention, a method for evaluating a C++ description by an IC includes the following steps. First, a C++ description including a C++ program is provided. Then, the C++ program is stored in a first memory module (e.g., a ROM, or the like) of an IC. Next, a scalar input and/or an input array may be provided to the IC. Then, the C++ program may be executed by a control device module of the IC. Next, a scalar output and/or an output array may be read from the IC.

摘要翻译： 本发明涉及基于C ++语言描述的IC实现的方法和装置。 在本发明的一个示例性方面，用于通过IC评估C ++描述的方法包括以下步骤。 首先，提供包括C ++程序的C ++描述。 然后，C ++程序被存储在IC的第一存储器模块（例如，ROM等中）中。 接下来，可以向IC提供标量输入和/或输入阵列。 然后，C ++程序可以由IC的控制装置模块执行。 接下来，可以从IC读取标量输出和/或输出阵列。

公开(公告)号：US06412102B1

公开(公告)日：2002-06-25

申请号：US09120617

申请日：1998-07-22

申请人： Alexander Andreev ,  Ivan Pavisic ,  Pedja Raspopovic

发明人： Alexander Andreev ,  Ivan Pavisic ,  Pedja Raspopovic

IPC分类号： G06F1750

CPC分类号： G06F17/5077

摘要： The invention is directed to optimization of an initial routing that connects nets on a surface, each of the nets including plural interconnected net pins. The surface is divided into a set of areas, and a boundary pin is defined at each point on a boundary of one of the areas where the boundary of the one of the areas intersects a net. Routing optimization is then performed in at least one of the areas, the routing optimization optimizing the routing among the net pins and the boundary pins within the at least one of the areas. The invention is also directed to optimization of an initial routing that connects nets on a surface, each of the nets including plural interconnected net pins. The surface is divided into a first set of pre-defined areas, and routing optimization is performed independently in each of the pre-defined areas in the first set. The surface is divided into a second set of pre-defined areas, and routing optimization is performed independently in each of the pre-defined areas in the second set. It is a feature of this aspect of the invention that each of plural pre-defined areas in the first set overlaps at least two pre-defined areas in the second set, and each of plural pre-defined areas in the second set overlaps at least two pre-defined areas in the first set.

摘要翻译： 本发明涉及一种将网络连接在一个表面上的初始路由的优化，每个网络包括多个互连的网络引脚。 表面被划分成一组区域，并且在一个区域的边界与网络相交的区域之一的边界上的每个点处定义边界销。 然后在至少一个区域中执行路由优化，路由优化优化网内引脚和该至少一个区域内的边界引脚之间的路由。 本发明还涉及将网络连接在表面上的初始路由的优化，每个网络包括多个互连的网络引脚。 表面被划分成第一组预定义区域，并且在第一组中的每个预定义区域中独立地执行路由优化。 表面被划分成第二组预定义区域，并且在第二组中的每个预定义区域中独立地执行路由优化。 本发明的这个方面的特征在于，第一组中的多个预定义区域中的每一个与第二组中的至少两个预定义区域重叠，并且第二组中的多个预定义区域中的每一个至少重叠 第一组中的两个预定义区域。

公开(公告)号：US06182272B2

公开(公告)日：2001-01-30

申请号：US09118661

申请日：1998-07-16

申请人： Alexander Andreev ,  Ivan Pavisic ,  Pedja Raspopovic

发明人： Alexander Andreev ,  Ivan Pavisic ,  Pedja Raspopovic

IPC分类号： G06F1750

CPC分类号： G06F17/5077

摘要： Routing layers are assigned to connection segments in integrated circuit design. A routing description that includes connection segments and a vertex where at least two of the connection segments connect to each other is obtained. A penalty is determined for the vertex based on a potential layer assignment combination for the connection segments that connect at the vertex, and routing layers are assigned to the connection segments based on the determined penalty.

摘要翻译： 路由层被分配到集成电路设计中的连接段。 获得包括连接段和至少两个连接段彼此连接的顶点的路由描述。 基于针对在顶点连接的连接段的潜在层分配组合，确定顶点的惩罚，并且基于确定的罚分将路由层分配给连接段。

公开(公告)号：US08286060B2

公开(公告)日：2012-10-09

申请号：US12182443

申请日：2008-07-30

申请人： Pavel A. Panteleev ,  Elyar E. Gasanov ,  Alexander Andreev ,  Ilya V. Neznanov ,  Pavel A. Aliseychik

发明人： Pavel A. Panteleev ,  Elyar E. Gasanov ,  Alexander Andreev ,  Ilya V. Neznanov ,  Pavel A. Aliseychik

IPC分类号： G06F11/00

CPC分类号： H03M13/1545 ,  H03M13/1515 ,  H03M13/153 ,  H03M13/1535 ,  H03M13/154 ,  H03M13/159

摘要： A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

摘要翻译： 一种在错误和擦除解码中产生擦除定位多项式的方法。 该方法通常包括以下步骤：（A）在当前时刻将当前值存储在多个寄存器中，（B）通过将每个当前值乘以多个常数中的相应一个来产生第一值，（C）至少通过门控产生第二值 除了具有擦除位置向量的多个擦除值中的当前一个值的第一值之外的所有值，（D）通过将第二值中的每一个与第一值中的相应一个组合来生成下一个值，（E）加载下一个 值代替寄存器代替下一时刻的当前值，（F）在最后时刻产生承载当前值的输出信号，使得当前值形成擦除定位器多项式的系数。

公开(公告)号：US20120161093A1

公开(公告)日：2012-06-28

申请号：US13271679

申请日：2011-10-12

申请人： Alexander Andreev ,  Sergey Gribok ,  Ranko Scepanovic

发明人： Alexander Andreev ,  Sergey Gribok ,  Ranko Scepanovic

IPC分类号： H01L47/00 ,  H01L23/52 ,  H01L29/84 ,  B82Y99/00

CPC分类号： H03K19/17728 ,  H03K19/17796

摘要： A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.

摘要翻译： 通孔可配置电路块可以包含可以或可以不通过可配置通孔互连的p型和n型晶体管链。 可配置的通孔也可用于将各种晶体管端子连接到接地线，电力线和/或可提供电路块外部的连接的各种端子。

公开(公告)号：US08181096B2

公开(公告)日：2012-05-15

申请号：US11957621

申请日：2007-12-17

申请人： Alexander Andreev ,  Ilya V. Neznanov ,  Elyar E. Gasanov ,  Pavel A. Panteleev

发明人： Alexander Andreev ,  Ilya V. Neznanov ,  Elyar E. Gasanov ,  Pavel A. Panteleev

IPC分类号： H03M13/03

CPC分类号： H03M13/154 ,  H03M13/1515

摘要： A method of configurable decoding is disclosed. The method generally includes the steps of (A) receiving a variable value in a configuration signal, (B) calculating a plurality of first syndromes corresponding to a particular codeword of a plurality of codewords received in an input signal, the particular codeword having a plurality of information symbols and a plurality of parity symbols coded such that up to a fixed value of a plurality of errors in the particular codeword are correctable, the fixed value being greater than the variable value, (C) transforming the first syndromes into a plurality of second syndromes such that no greater than the variable value of the errors in the particular codeword are correctable and (D) generating an intermediate signal carrying the second syndromes.

摘要翻译： 公开了一种可配置解码的方法。 该方法通常包括以下步骤：（A）在配置信号中接收可变值，（B）计算对应于在输入信号中接收的多个码字的特定码字的多个第一校正子，所述特定码字具有多个 信息符号和多个奇偶校验符号进行编码，使得特定码字中的多个错误的固定值可修正，该固定值大于可变值，（C）将第一校正子变换为多个 第二综合征，使得不大于特定码字中的错误的可变值是可校正的，并且（D）产生携带第二综合征的中间信号。

公开(公告)号：US08035537B2

公开(公告)日：2011-10-11

申请号：US12138920

申请日：2008-06-13

申请人： Alexander Andreev ,  Sergey Gribok ,  Oleg Izyumin ,  Ranko Scepanovic ,  Igor Vikhliantsev ,  Vojislav Vukovic

发明人： Alexander Andreev ,  Sergey Gribok ,  Oleg Izyumin ,  Ranko Scepanovic ,  Igor Vikhliantsev ,  Vojislav Vukovic

IPC分类号： H03M7/00

CPC分类号： H03M13/296 ,  H03M13/2725 ,  H03M13/6508 ,  H03M13/6513 ,  H03M13/6519 ,  H03M13/6525 ,  H03M13/6544 ,  H03M13/6569

摘要： Methods and apparatus are provided for programmable decoding of a plurality of code types. A method is provided for decoding data encoded using one of a plurality of code types, where each of the code types correspond to a communication standard. The code type associated with the data is identified and the data is allocated to a plurality of programmable parallel decoders. The programmable parallel decoders can be reconfigured to decode data encoded using each of the plurality of code types. A method is also provided for interleaving data among M parallel decoders using a communications network. An interleaver table is employed, wherein each entry in the interleaver table identifies one of the M parallel decoders as a target decoder and a target address of a communications network for interleaved data. Data is interleaved by writing the data to the target address of the communications network. The communications network can comprise, for example, a cross-bar switch and/or one or more first-in-first-out buffers.

摘要翻译： 提供了用于多种代码类型的可编程解码的方法和装置。 提供了一种用于解码使用多种代码类型之一编码的数据的方法，其中每种代码类型对应于通信标准。 识别与数据相关联的代码类型，并将数据分配给多个可编程并行解码器。 可重新配置可编程并行解码器以对使用多种代码类型中的每一种编码的数据进行解码。 还提供了一种用于使用通信网络在M个并行解码器之间交织数据的方法。 使用交织器表，其中交织器表中的每个条目将M个并行解码器中的一个识别为目标解码器，并将交织数据的通信网络的目标地址标识。 通过将数据写入到通信网络的目标地址来交织数据。 通信网络可以包括例如交叉开关和/或一个或多个先入先出缓冲器。

公开(公告)号：US20100162071A1

公开(公告)日：2010-06-24

申请号：US12339667

申请日：2008-12-19

申请人： Alexander Andreev ,  Vojislav Vukovie ,  Igor Vikhliantsev

发明人： Alexander Andreev ,  Vojislav Vukovie ,  Igor Vikhliantsev

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1137 ,  H03M13/1122 ,  H03M13/116

摘要： A parity unit circuit for use in a parallel, pipelined, low density parity check (LDPC) decoder that implements an iterative, min-sum, message passing LDPC algorithm. The parity unit provides a memory logic block for storing information relating to a current and next iteration of the LDPC computations and includes a “compute 1” logic block for computing a parity message (with sign) for application to related bit nodes and a “compute2” logic block for updating the data stored in the memory logic block for a next iteration of the LDPC decoder.

摘要翻译： 一种用于并行，流水线，低密度奇偶校验（LDPC）解码器的奇偶校验单元电路，其实现迭代的最小和消息传递LDPC算法。 奇偶校验单元提供用于存储与LDPC计算的当前和下一次迭代有关的信息的存储器逻辑块，并且包括用于计算应用于相关比特节点的奇偶校验消息（具有符号）的“计算1”逻辑块，以及“计算2” “逻辑块，用于更新存储在存储器逻辑块中的数据，用于LDPC解码器的下一次迭代。

公开(公告)号：US20100031127A1

公开(公告)日：2010-02-04

申请号：US12182443

申请日：2008-07-30

申请人： Pavel A. Panteleev ,  Elyar E. Gasanov ,  Alexander Andreev ,  Ilya V. Neznanov ,  Pavel A. Aliseychik

发明人： Pavel A. Panteleev ,  Elyar E. Gasanov ,  Alexander Andreev ,  Ilya V. Neznanov ,  Pavel A. Aliseychik

IPC分类号： H03M13/15 ,  G06F11/10

CPC分类号： H03M13/1545 ,  H03M13/1515 ,  H03M13/153 ,  H03M13/1535 ,  H03M13/154 ,  H03M13/159

摘要： A method to generate an erasure locator polynomial in an error-and-erasure decode. The method generally includes the steps of (A) storing current values in multiple registers at a current moment, (B) generating first values by multiplying each current value by a respective one of multiple constants, (C) generating second values by gating at least all but one of the first values with a current one of multiple erasure values of an erasure position vector, (D) generating next values by combining each one of the second values with a corresponding one of the first values, (E) loading the next values into the registers in place of the current values at a next moment and (F) generating an output signal carrying the current values at a last moment such that the current values form the coefficients of the erasure locator polynomial.

摘要翻译： 一种在错误和擦除解码中产生擦除定位多项式的方法。 该方法通常包括以下步骤：（A）在当前时刻将当前值存储在多个寄存器中，（B）通过将每个当前值乘以多个常数中的相应一个来产生第一值，（C）至少通过门控产生第二值 除了具有擦除位置向量的多个擦除值中的当前一个值的第一值之外的所有值，（D）通过将第二值中的每一个与第一值中的相应一个组合来生成下一个值，（E）加载下一个 值代替寄存器代替下一时刻的当前值，（F）在最后时刻产生承载当前值的输出信号，使得当前值形成擦除定位器多项式的系数。

公开(公告)号：US20090158118A1

公开(公告)日：2009-06-18

申请号：US11957621

申请日：2007-12-17

申请人： Alexander Andreev ,  Ilya V. Neznanov ,  Elyar E. Gasanov ,  Pavel A. Panteleev

发明人： Alexander Andreev ,  Ilya V. Neznanov ,  Elyar E. Gasanov ,  Pavel A. Panteleev

IPC分类号： H03M13/13 ,  G06F11/10

CPC分类号： H03M13/154 ,  H03M13/1515

摘要： A method of configurable decoding is disclosed. The method generally includes the steps of (A) receiving a variable value in a configuration signal, (B) calculating a plurality of first syndromes corresponding to a particular codeword of a plurality of codewords received in an input signal, the particular codeword having a plurality of information symbols and a plurality of parity symbols coded such that up to a fixed value of a plurality of errors in the particular codeword are correctable, the fixed value being greater than the variable value, (C) transforming the first syndromes into a plurality of second syndromes such that no greater than the variable value of the errors in the particular codeword are correctable and (D) generating an intermediate signal carrying the second syndromes.

摘要翻译： 公开了一种可配置解码的方法。 该方法通常包括以下步骤：（A）在配置信号中接收可变值，（B）计算对应于在输入信号中接收的多个码字的特定码字的多个第一校正子，所述特定码字具有多个 信息符号和多个奇偶校验符号进行编码，使得特定码字中的多个错误的固定值可修正，该固定值大于可变值，（C）将第一校正子变换为多个 第二综合征，使得不大于特定码字中的错误的可变值是可校正的，并且（D）产生携带第二综合征的中间信号。